Gate Driver Clamp Circuit for Negative Transient Overvoltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The interface between an n-type epitaxial structure and a p-type substrate in gate drivers can lead to unwanted current flow due to an active diode, potentially damaging the gate driver and integrated circuit, especially during negative transient events that cause overcharging by bootstrap capacitors.
Innovation Solution
A clamp circuit is introduced to limit the voltage provided to external devices by connecting a first node to a second node and including transistors and drivers configured to receive clamp voltage, ensuring the output voltage does not exceed the clamp voltage minus the gate-to-source voltage of the transistors, thereby preventing overcharging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gate driver is fabricated in an n-type epitaxial structure on a p-type substrate forming a diode interface, then the gate driver can be integrated in a standard IC process, but unwanted current may flow through the diode during negative transients causing damage
Solution Approach 1:
The patent introduces a clamp circuit as an intermediary component between the bootstrap capacitor and the external transistor gate. This clamp circuit includes a diode and resistor that actively intervene to limit voltage excursions and prevent unwanted current flow through the substrate diode during negative transients, thereby protecting the IC while maintaining standard fabrication processes.
2Ease of operation
If the bootstrap capacitor provides voltage to the external transistor gate, then the transistor can be properly biased and operated, but negative transients may cause overcharging and destroy the external transistor
Solution Approach 1:
The clamp circuit is configured to activate before the negative transient can cause damaging overcharging of the external transistor gate. The diode in the clamp circuit conducts when the bootstrap capacitor voltage drops below a certain threshold, providing a discharge path that cushions against further voltage drops and prevents the gate voltage from exceeding safe limits during transient events.
3Power
If no voltage limiting mechanism is used, then the gate driver can provide full voltage swing to external devices, but the output voltage may exceed safe levels and damage external devices
Solution Approach 1:
The clamp circuit provides automatic feedback control by monitoring the voltage at the gate of the external transistor through the diode-resistor network. When the voltage exceeds the clamp voltage minus the diode forward voltage, the diode conducts and actively clamps the voltage, creating a self-regulating mechanism that limits output voltage without requiring external control circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The clamp circuit effectively mitigates the effects of negative transients, preventing overcharging and potential damage to external devices by limiting the voltage to a safe level, thus protecting the gate driver and integrated circuit.
Implementation Method 1
The clamp circuit is configured to provide a clamp voltage. The first transistor has a gate-to-source voltage and an output voltage of the circuit output does not exceed the clamp voltage less the gate-to-source voltage of the first transistor.
Data Source
AI summary
In one aspect, a gate driver circuit includes a clamp circuit connecting a first node to a second node. The clamp circuit is configured to provide a clamp voltage. The gate driver circuit also includes a first driver connected to the first node and to the second node. The first driver comprising a first input configured to receive the clamp voltage from the clamp circuit. The gate driver circuit further includes a first transistor having a drain connected to the first node, a source connected to a circuit output and a gate connected to an output of the first driver. The first transistor has a gate-to-source voltage and an output voltage of the circuit output does not exceed the clamp voltage less the gate-to-source voltage of the first transistor.