Gate Driver Circuit Clock Signal Coordination
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Solution Overview
Problem
As screen sizes, resolutions, and refresh rates for electronic displays increase, providing gate signals to each row of pixels becomes more challenging due to limited time for the gate driver circuit to receive clock signals, leading to the need for overlapping gate enable signals, which increases the number of circuit components and power consumption.
Innovation Solution
The gate driver circuit reduces the number of clocks used by employing a gate signal from a previous row of pixels or another gate driver circuit to initiate pre-charging, allowing it to coordinate gate signals more efficiently and minimize additional circuit components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If additional clocks are used to coordinate gate signals for higher resolution and refresh rates, then the display can depict image data more effectively, but the device complexity and power consumption increase
Solution Approach 1:
The patent applies multi-functionality by enabling a single clock signal to serve multiple purposes: it coordinates both the pre-charging phase and the gate signal output phase. The gate driver circuit is designed to reuse the same clock signal for different operational stages, eliminating the need for separate dedicated clocks for each function, thereby reducing overall circuit complexity while maintaining high-resolution and high-refresh-rate display capabilities
Solution Approach 2:
The patent implements preliminary action by pre-charging the gate node before the actual gate signal is needed. This pre-charging is coordinated using the same clock signal that will later drive the gate output, allowing the circuit to prepare in advance using existing timing resources rather than requiring additional dedicated pre-charge clocks, thus reducing complexity while ensuring timely switch activation
2Productivity
If additional clocks are used to coordinate gate signals for higher refresh rates, then the display can operate at faster refresh rates, but the power consumption increases
Solution Approach 1:
The patent reduces power consumption by making the clock signal multi-functional, using it for both pre-charging coordination and gate signal timing. This eliminates the need for additional high-frequency clocks that would consume extra power, allowing the circuit to achieve high refresh rates using a single clock source operating at the required frequency rather than multiple lower-frequency clocks
Solution Approach 2:
The patent merges the timing functions for pre-charging and gate signal output into a single clock signal. By combining these previously separate timing functions into one unified clock source, the circuit reduces the total number of active clock generators and their associated power consumption, while still maintaining the ability to operate at high refresh rates required for modern displays
3Productivity
If additional circuit components are added to provide overlapped enable gate signals, then the gate driver circuit can handle larger screen sizes and higher resolutions, but the area occupied by the circuit increases
Solution Approach 1:
The patent applies multi-functionality by designing the gate driver circuit to use the same clock signal for multiple operational phases (pre-charge and gate output). This eliminates the need for separate dedicated clock circuits and associated control logic that would otherwise be required to coordinate overlapping gate signals for large high-resolution displays, thereby reducing the overall circuit footprint while maintaining the capability to drive larger screens at higher resolutions
Solution Approach 2:
The patent extracts and eliminates redundant clock circuitry from the gate driver design. By recognizing that separate pre-charge clocks can be replaced by repurposing the main gate clock signal, the design removes unnecessary components and simplifies the overall circuit architecture, reducing the area occupied by the gate driver while preserving the ability to handle large screen sizes and high resolutions
Data Source
AI summary
A display device may include a plurality of rows of pixels configured to display image data on a display and a first gate driver circuit. The first gate driver circuit may couple a first voltage source to a first node associated with a first gate of a first switch upon receipt of a start signal or a gate signal from another gate driver circuit and couple a first clock signal to a first gate line via the first switch after a first voltage of the first node exceeds a threshold. The threshold is associated with activating the first switch, such that the first gate line is configured to couple to a first row of the plurality of rows of pixels. The first gate driver circuit may then couple a second voltage source to the first node based on a second clock signal, such that the second voltage source discharges the first node.