Gate Driver Clock Signal Discharge for Display Panel Brightness Uniformity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In liquid crystal displays, the first gate signal is distorted due to a high start signal period longer than the horizontal scanning period, leading to malfunction and uneven pixel brightness, where the first pixel row appears brighter than others.
Innovation Solution
The gate driver outputs gate signals with a first clock signal having a longer high period and a second clock signal with an opposite phase, ensuring the first gate signal is discharged before data signals are applied, and includes a dummy stage to prevent distortion, with specific transistor configurations to enhance discharge capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a start signal with a high period longer than the horizontal scanning period is applied to the first stage, then the gate driver can be simplified in structure, but the first gate signal becomes distorted and cannot be discharged to a low level in time
Solution Approach 1:
The patent applies different clock signal parameters to different gate lines. Specifically, odd-numbered gate lines receive clock signals with one period while even-numbered gate lines receive clock signals with a different period, allowing localized optimization of signal discharge timing for each gate line based on its specific requirements.
Solution Approach 2:
The patent introduces dynamic control of clock signal periods to adapt to the discharge requirements of different gate signals. The clock generator dynamically adjusts the period of clock signals based on which gate line needs discharge, making the system adaptable rather than static.
2Ease of operation
If the first gate signal is not discharged to a low level before data signal polarity inversion, then the gate driver operation is simplified, but pixel brightness becomes uneven with the first pixel row appearing brighter
Solution Approach 1:
The patent performs preliminary discharge of the first gate signal to a low level before the data signal polarity inversion occurs. This preliminary action ensures that the gate signal is properly discharged in advance, preventing the brightness malfunction that would otherwise occur during the polarity inversion process.
Solution Approach 2:
The patent applies a counter-phase clock signal to prevent the harmful effect of incomplete gate signal discharge. By using a clock signal with opposite phase timing, the system proactively counteracts the potential brightness issue before it manifests.
3Device complexity
If a single clock signal period is used for all gate lines, then the clock generator is simplified, but some gate signals cannot be discharged in time during polarity inversion
Solution Approach 1:
The patent segments the clock signal generation into different periods for different gate lines. Instead of using a single unified clock period, the system divides the clock signaling into multiple period configurations, allowing each gate line to receive appropriately timed clock signals for proper discharge.
Solution Approach 2:
The patent employs asymmetric clock signal periods where odd-numbered gate lines receive clock signals with one period and even-numbered gate lines receive clock signals with a different period. This asymmetric approach optimizes discharge timing for each group of gate lines based on their specific operational requirements.
Data Source
AI summary
A display apparatus includes a gate driver which sequentially outputs a gate signal at a high state in response to a gate control signal and a data driver which converts image data into a data signal in response to a data control signal. The display apparatus further includes a display panel which includes a plurality of gate lines which sequentially receive the gate signal, a plurality of data lines which receive the data signal and a plurality of pixels connected to the gate and data lines and which receive the data signal in response to the gate signal to display an image. The polarity of the data signal is inverted after the gate signal transitions to a low state.