Gate Driver Clock Signal Duty Ratio Adjustment for Power Reduction
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Solution Overview
Problem
Conventional liquid crystal display (LCD) apparatuses face challenges in maintaining display quality and preventing deterioration due to the degradation of gate driving circuits, particularly the amorphous silicon gate (ASG) type, which affects the stability and efficiency of the driver circuits.
Innovation Solution
The proposed display apparatus incorporates a gate driver and gate controller that generate gate signals with specific voltage levels and clock signals, including a duty ratio adjustment and phase control during the vertical blanking period, to reduce power consumption and prevent transistor degradation, while maintaining a similar waveform to the active period for minimized load change and reduced power supply ripple noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the clock signal maintains a high duty ratio during the vertical blanking period, then the gate driver operates continuously, but electrical power consumption increases and transistor degradation accelerates
Solution Approach 1:
The patent applies periodic action by adjusting the clock signal duty ratio dynamically between active and blanking periods. During the vertical blanking period, the duty ratio is reduced compared to the active period, creating a periodic modulation pattern that reduces power consumption while maintaining necessary driver operation. This is achieved by controlling the clock signal to have different high-level durations in different phases of the frame cycle.
Solution Approach 2:
The patent implements dynamics by making the clock signal characteristics variable rather than fixed. The duty ratio of the clock signal is dynamically adjusted based on the operating phase (active vs. blanking period), allowing the gate driver to adapt its operation to reduce power consumption during periods when full performance is not required, while maintaining reliability during critical display updating periods.
2Reliability
If the clock signal amplitude is increased during the vertical blanking period, then signal strength is maintained, but power supply ripple noise increases
Solution Approach 1:
The patent applies parameter changes by carefully controlling the clock signal's voltage levels and duty ratio during the vertical blanking period. The high level of the clock signal in the blanking period is set to be lower than in the active period, and the duty ratio is adjusted to minimize fluctuations in power supply current. These parameter optimizations reduce power supply ripple noise while maintaining sufficient signal strength for reliable gate driver operation.
3Speed
If the gate driver operates at full capacity during the vertical blanking period, then display response time is reduced, but transistor degradation accelerates
Solution Approach 1:
The patent applies periodic action by varying the operation intensity of the gate driver between active and blanking periods. During the vertical blanking period, when no display updating is needed, the clock signal duty ratio is reduced, causing the gate driver to operate at lower capacity. This periodic modulation reduces transistor stress and degradation during the blanking period while maintaining full performance during the active period when display response is critical.
Solution Approach 2:
The patent implements partial action by providing just sufficient clock signal activity during the vertical blanking period to maintain basic driver functionality without excessive operation. The reduced duty ratio ensures that the gate driver operates at partial capacity during the blanking period, which is adequate for maintaining transistor health and extending lifespan, while full capacity operation is reserved for the active period when maximum performance is required.
Data Source
AI summary
A display apparatus includes a display panel comprising a pixel which is connected to a gate line and a data line, a gate driver configured to generate a gate signal having a gate-on voltage and a gate-off voltage and to provide the gate line with the gate signal, and a gate controller configured to generate a clock signal having a duty ratio and to provide the gate driver with the clock signal, where a mean amplitude of the clock signal in a vertical blanking period of a frame cycle is smaller than the mean amplitude of the clock signal in an active period of the frame cycle.