Built-In Gate Driver Clock Layout for Lower Output Delay
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Solution Overview
Problem
Existing built-in gate drivers for flat panel display devices face output delay issues due to clock delay caused by resistance and parasitic capacitance of clock lines, particularly the overlap capacitance between clock and power lines, which affects the performance of gate drivers.
Innovation Solution
The solution involves dividing clock lines into first and second clock groups based on usage and arranging them on both sides of the shift register, reducing overlap area and load on each clock line, thereby decreasing clock and output delays. This is achieved by separating the clock groups into distinct layers with insulating layers in between, minimizing overlap capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If clock lines and power lines are arranged in parallel at the outer side of the shift register, then the layout is simple and easy to manufacture, but the overlap capacitance between clock lines and power lines increases, causing increased clock delay and output delay
Solution Approach 1:
The clock lines are divided into first and second clock groups, with the first clock group arranged at a first side of the shift register and the second clock group arranged at a second side of the shift register. This segmentation reduces the overlap capacitance between clock lines and power lines, thereby decreasing clock delay and output delay while maintaining manufacturing feasibility.
Solution Approach 2:
The patent utilizes spatial distribution by arranging clock groups at different sides (dimensions) of the shift register rather than simply parallel arrangement. This dimensional change in layout reduces parasitic capacitance effects while maintaining the electrical connection requirements.
2Device complexity
If clock lines are arranged parallel to power lines, then the device complexity is reduced, but the parasitic capacitance of clock lines increases due to overlap with power lines, affecting gate driver performance
Solution Approach 1:
By segmenting clock lines into two groups and distributing them at different sides of the shift register, the patent reduces the total overlap area between clock lines and power lines. This segmentation strategy maintains relatively simple device structure while significantly reducing parasitic capacitance.
Solution Approach 2:
The patent applies different spatial arrangements to different clock groups based on their specific requirements. The first clock group is arranged at the first side and the second clock group at the second side, optimizing the local layout to minimize parasitic capacitance for each group while maintaining overall device simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the load on each clock line, decreases clock delay, and improves output characteristics of the gate driver by minimizing overlap capacitance between clock lines, leading to enhanced performance in flat panel display devices.
Implementation Method 1
the parasitic capacitance of a clock line includes parasitic capacitance of an output TFT connected to the clock line and an overlap capacitance caused by overlap between the clock line or another clock line and a power line
Data Source
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AI summary
Discussed are a built-in gate driver capable of improving output characteristics of the gate driver by reducing load of clock lines and a display device using the same. The built-in gate driver can include a shift register, a first clock group and a second clock group located in a non-display region of a display panel. The shift register includes a plurality of stages for individually driving gate lines of a display region. The first clock group includes clock lines arranged at a first side of the shift register. The second clock group includes clock lines arranged at a second side of the shift register. Each of the clock lines includes a main line and a branch line branched from the main line and connected to a corresponding stage. A branch line belonging to a corresponding clock group of any one of the first and second clock groups does not overlap a main line belonging to the other clock group.