Gate Driver Clock Line Layout for OLED Voltage Stability
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Solution Overview
Problem
OLED display devices experience luminance degradation over time due to organic light emitting diode degradation, leading to variations in voltage stored in storage capacitors, which existing technologies fail to address effectively.
Innovation Solution
A gate driver design that includes a first scan driver and a first sensing driver, with specific configurations of scan and sensing clock lines to reduce voltage variation by pulling down the scan signal output more rapidly than the sensing signal output, minimizing voltage loss in storage capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the scan signal output is pulled down rapidly to maintain storage capacitor voltage, then voltage variation is reduced, but the sensing signal output cannot be pulled down as rapidly, causing voltage loss
Solution Approach 1:
The gate driver is divided into separate scan driver and sensing driver units, each with independent clock lines. This segmentation allows the scan signal to be pulled down rapidly through the scan driver while the sensing signal maintains its voltage through the sensing driver, resolving the contradiction between rapid pull-down speed and voltage stability.
Solution Approach 2:
Different clock line configurations are applied to different parts of the gate driver. The scan clock line is designed for rapid signal transition, while the sensing clock line is designed for voltage stability. This local differentiation allows each signal type to have optimized characteristics without compromising the other.
2Speed
If the scan clock line is positioned closer to the scan driver than the sensing clock line, then scan signal transmission is improved, but the sensing clock line becomes relatively farther from the sensing driver
Solution Approach 1:
The clock line layout is designed asymmetrically, with the scan clock line positioned closer to the scan driver and the sensing clock line positioned closer to the sensing driver. This asymmetric arrangement optimizes the scan signal transmission speed while compensating for the sensing clock line length through the sensing driver's proximity.
Solution Approach 2:
The clock lines are arranged in different spatial dimensions and orientations. The scan clock line extends in one direction from the scan driver, while the sensing clock line extends in another direction from the sensing driver. This dimensional separation allows both lines to have optimal characteristics despite the asymmetric positioning.
Data Source
AI summary
There are provided a gate driver and a display device including the same. The gate driver includes: a first scan driver; a first sensing driver; a first scan clock line; and a first sensing clock line. The first scan clock line includes a first scan clock main line extending in one direction, and a first scan clock connection line connected to the first scan clock main line and the first scan driver. The first sensing clock line includes a first sensing clock main line extending in one direction, and a first sensing clock connection line connected to the first sensing clock main line and the first sensing driver. The first scan clock main line is closer to each of the first scan driver and the first sensing driver than the first sensing clock main line.