Gate Driver Clock Signal Phase Matching for Line Mura Suppression
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Solution Overview
Problem
Display panels face issues with line mura generation when switching from partial driving mode to normal driving mode due to differences in stress applied to gate drivers connected to pixels that have been turned on versus those turned off, leading to delayed waveforms and increased rise and fall times.
Innovation Solution
A display panel design with a gate driver that includes a first and second clock signal line, both with the same phase, applied to stages connected to different areas of the panel, ensuring similar deterioration and reducing load differences, thereby suppressing line mura generation during mode switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If pixels in a partial area are turned off to achieve high-speed driving, then driving speed is improved, but line mura occurs at the boundary between turned-on and turned-off pixel areas due to stress difference
Solution Approach 1:
The patent applies preliminary action by turning on pixels in the first area (which would normally be turned off during partial driving) before switching from partial to normal driving mode. This preliminary action equalizes the stress condition between the first and second areas, preventing line mura from occurring at the boundary when normal driving mode is activated.
2Adaptability or versatility
If gate driver stages are subjected to different stress conditions, then partial driving mode is achieved, but waveform delay and increased rise/fall times occur
Solution Approach 1:
The patent applies equipotentiality by making both the first and second clock signal lines have the same phase, ensuring that gate driver stages in both areas operate under equivalent timing conditions. This equalizes the stress and operational state of the gate driver stages, preventing waveform delay and maintaining signal quality when switching between driving modes.
Data Source
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AI summary
A display panel comprises a substrate including a first area and a second area, a gate driver configured to supply a gate signal to pixels disposed on the substrate, a plurality of stages constituting the gate driver, and a first clock signal line and a second clock signal line to be respectively applied with a first clock signal and a second clock signal having the same phase. The plurality of stages are connected to the first area and the second area and driven at the same time. The first clock signal line and the second clock signal line are connected to each of the plurality of stages connected to the first area and the second area.