Gate Driver Clock Reconfiguration for Compact Dual-Rate Scanning
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Solution Overview
Problem
Gate drivers that implement both normal and high scan rate modes face an increase in mount area, limiting their application in display devices.
Innovation Solution
A gate driver design incorporating a level shifter and gate shift register that outputs synchronized gate clocks with specific phase differences and pulse widths, allowing for both normal and high scan rate modes without increasing the mount area, using 16-phase clocks for both modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a gate driver is designed to implement both normal scan rate mode and high scan rate mode, then the scan rate versatility is improved, but the mount area increases
Solution Approach 1:
The gate driver is designed with a universal architecture that can operate in both normal scan rate mode and high scan rate mode using the same 16-phase clock structure. The level shifter and gate shift register are configured to generate appropriate gate clocks and scan signals for either mode without requiring separate dedicated circuits, thereby achieving multi-functionality while maintaining compact size.
Solution Approach 2:
The gate driver switches between operating modes by changing the phase difference parameter of the gate clocks. In normal scan rate mode, adjacent gate clocks have a phase difference of 1 horizontal period, while in high scan rate mode, adjacent gate clock pairs maintain the same phase relationship. This parameter-based mode switching allows versatility without increasing mount area.
2Reliability
If the gate driver uses different clock configurations for normal and high scan rate modes, then the scan output quality is improved, but the device complexity increases
Solution Approach 1:
The gate driver employs dynamic configuration where the same 16-phase clock structure is adaptively reconfigured for different modes. The level shifter dynamically adjusts the gate clock generation based on the operating mode, and the gate shift register dynamically shifts signals accordingly. This dynamic adaptability maintains scan output quality while avoiding the complexity of static dual-configurations.
Solution Approach 2:
The clock system is segmented into 16 phases that can be selectively grouped and configured. For normal scan rate, all 16 phases are used sequentially with 1 horizontal period phase differences. For high scan rate, the phases are grouped into pairs that are synchronized, effectively creating a compressed timing structure. This segmentation allows quality scan output in both modes without complex dedicated circuits.
3Stability of the object's composition
If adjacent gate clocks have larger phase differences to reduce ripple effects, then the scan signal stability is improved, but the timing margin for high scan rate mode decreases
Solution Approach 1:
The gate driver applies partial synchronization in high scan rate mode where adjacent gate clock pairs maintain the same phase relationship, providing enough stability for reliable scanning while not over-synchronizing which would consume excessive timing margin. This partial action approach achieves the right balance between stability and timing availability.
Solution Approach 2:
The phase difference parameter is changed based on operating mode: in normal scan rate mode, adjacent gate clocks have 1 horizontal period phase difference for maximum stability; in high scan rate mode, adjacent gate clock pairs are synchronized (0 phase difference within pairs) while maintaining progression between pairs. This parameter adaptation optimizes both stability and timing margin for each mode.
Data Source
AI summary
A gate driver can include a level shifter configured to output first-mode gate clocks in a normal scan rate mode and output second-mode gate clocks in a high scan rate mode, and a gate shift register configured to output normal scan rate scan signals synchronized with the first-mode gate clocks in the normal scan rate mode and output high scan rate scan signals synchronized with the second-mode gate clocks in the high scan rate mode. Adjacent gate clocks of the first-mode gate clocks have a phase difference equal to 1 horizontal period, and adjacent gate clock pairs of the second-mode gate clocks have a phase difference equal to 1 horizontal period and two gate clocks configuring the same gate clock pair are synchronized with each other. The first-mode gate clocks are implemented as a 16-phase clock and the second-mode gate clocks are implemented as a 16-phase clock.