Gate Driver Circuit Resetting via Clock Signal Lines
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Solution Overview
Problem
Existing gate driver circuits for display devices require additional elements and TFTs to reset shift registers, leading to increased bezel width and production costs, which hinders the achievement of a narrow bezel design and affects image quality.
Innovation Solution
A gate driver circuit design that utilizes clock signal lines to provide resetting signals to shift registers, eliminating the need for additional resetting units or TFTs, thereby simplifying the circuit structure and allowing for a narrow bezel display device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional shift registers with self-resetting function are used to reset the last shift register, then the resetting function is achieved, but the space occupied by the gate driver circuit increases
Solution Approach 1:
The clock signal lines are designed to serve dual purposes: providing clock signals during the display stage and providing resetting signals during the resetting stage. This multi-functionality eliminates the need for separate resetting units or additional TFTs, thereby achieving the resetting function without increasing the circuit space
Solution Approach 2:
The patent merges the clock signal provision function and the resetting signal provision function into the same clock signal lines. By combining these functions, the circuit structure is simplified and the space occupation is reduced while maintaining reliable resetting capability
2Reliability
If additional resetting signal line is used to reset the last shift register, then the resetting function is achieved, but the bezel width increases
Solution Approach 1:
The clock signal lines are designed to serve dual purposes: providing clock signals during the display stage and providing resetting signals during the resetting stage. This multi-functionality eliminates the need for separate resetting signal lines, thereby achieving the resetting function without increasing the bezel width
3Reliability
If additional shift registers with self-resetting function are used, then the resetting function is achieved, but the number of TFTs increases
Solution Approach 1:
The clock signal lines are designed to serve dual purposes: providing clock signals during the display stage and providing resetting signals during the resetting stage. This multi-functionality eliminates the need for additional TFTs in self-resetting shift registers, thereby achieving the resetting function without increasing the TFT count
Solution Approach 2:
The patent merges the clock signal provision function and the resetting signal provision function into the same clock signal lines, eliminating the need for additional TFTs that would be required for separate resetting units
Data Source
AI summary
The present disclosure provides a gate driver circuit including at least one set of clock signal lines and multiple levels of shift registers arranged in a cascaded manner. Each set of the clock signal lines includes two clock signal lines. The multiple levels of shift registers is divided into at least one set, and each set of the clock signal lines corresponds to a set of the shift registers. One clock signal line in each set of the clock signal lines is connected to a resetting signal input end of a last-level shift register in the set of the shift registers corresponding to the set of the clock signal lines. The present disclosure further provides an array substrate, a display device and a method for driving the gate driver circuit.