Gate Driver Clock Signal Segmentation for Power Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The power consumption of gate drivers in display devices increases with the load on clock signals, leading to higher energy expenditure.
Innovation Solution
A gate driver design that includes multiple stages receiving clock signals, where each stage has specific terminals for clock, carry, and output signals, allowing for optimized signal propagation and reduced power consumption by increasing the period of each clock signal and decreasing the capacitance viewed from the clock lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the number of stages receiving clock signals is increased, then the power consumption is reduced, but the device complexity increases
Solution Approach 1:
The gate driver is divided into multiple stages (first stage, second stage, third stage, fourth stage, etc.), where each stage receives specific clock signals and generates corresponding gate signals. This segmentation allows the system to reduce power consumption by distributing the clock signal load across multiple stages rather than using a single high-load configuration.
2Use of energy by moving object
If the frequency of clock signals is reduced, then the power consumption is reduced, but the productivity decreases
Solution Approach 1:
Different clock signals (first clock signal, second clock signal, third clock signal, fourth clock signal, etc.) are applied periodically to different stages with non-overlapping activation periods. The activation period of each clock signal does not overlap with others, creating a periodic action pattern that reduces instantaneous power consumption while maintaining overall productivity through coordinated operation of multiple stages.
3Use of energy by moving object
If the capacitance of equivalent capacitors viewed from clock lines is decreased, then the power consumption is reduced, but the measurement precision may be affected
Solution Approach 1:
Each stage is designed with specific local characteristics in terms of capacitance loading on clock lines. The equivalent capacitance viewed from each clock line is optimized locally for that particular stage's operation, allowing reduced power consumption without compromising the overall signal integrity and timing precision required for gate signal generation.
Data Source
AI summary
A gate driver including: first to N-th stages receiving first to N-th clock signals from first to N-th clock lines, the first stage includes a first clock terminal receiving the first clock signal, a second clock terminal receiving a second clock signal, a carry terminal receiving a vertical start signal, and an output terminal outputting a first gate signal, an N−K-th stage includes a first clock terminal receiving an N−K-th clock signal, a second clock terminal receiving an N−K+1-th clock signal, a carry terminal receiving an N−K−1-th gate signal, and an output terminal outputting an N−K-th gate signal, and the N-th stage includes a first clock terminal receiving the N-th clock signal, a second clock terminal receiving the first clock signal, a carry terminal receiving an N−1-th gate signal, and an output terminal outputting an N-th gate signal.