Integrated Gate Driver Power Reduction via Clock Signal Segmentation
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Solution Overview
Problem
Integrated gate drivers in display panels face high power consumption due to large parasitic capacitance, which increases manufacturing costs and reduces efficiency.
Innovation Solution
Implementing a gate driver configuration where clock signals are divided into two stage groups, with one group's signals not swung during a certain time period in one frame, reducing power usage across stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gate driver is integrated with the panel by being patterned along with gate lines, data lines, and thin film transistors, then manufacturing costs are reduced by eliminating the need for additional gate driving chips, but power consumption increases due to large parasitic capacitance from the large number of thin film transistors with large sizes
Solution Approach 1:
The gate driver is divided into multiple stages, where each stage drives a specific gate line. This segmentation allows for optimized transistor sizing in each stage, reducing the overall parasitic capacitance while maintaining the integrated structure's manufacturing cost advantage.
Solution Approach 2:
The invention changes the operating parameters of the gate driver by using non-swing clock signals for certain stages during specific time periods. This parameter change reduces the dynamic power consumption caused by parasitic capacitance charging and discharging, while the integrated structure remains intact for cost efficiency.
2Productivity
If clock signals are applied to all stages continuously, then the gate driver can drive all gate lines, but power consumption increases due to continuous voltage swing of clock signals charging and discharging parasitic capacitance
Solution Approach 1:
The invention implements periodic action by applying non-swing clock signals to certain stages during specific time periods (e.g., during horizontal blanking intervals). This allows the gate driver to maintain full functionality when needed while reducing power consumption during periods when certain gate lines do not require updates.
Solution Approach 2:
The gate driver dynamically adjusts its operation by switching between swing and non-swing clock signal modes for different stages based on real-time requirements. This dynamic operation optimizes the balance between productivity and energy loss by activating full driving capability only when necessary.
Data Source
AI summary
An exemplary embodiment of the present invention provides a display panel including: a display area configured to include a gate line and a data line; and a gate driver connected to one terminal of the gate line, the gate driver including a plurality of stages and being integrated on a substrate to output a gate voltage. The stages are divided into at least two stage groups, a first pair of clock signals including a first clock signal and a first clock-bar signal is applied to a first one of the stage groups, and the first pair of clock signals is not swung for a time period in one frame.