Gate Driver Clock Signal Sharing for Display Area Reduction
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Solution Overview
Problem
The existing gate drivers for organic light emitting display devices face challenges with increased load and size due to the need for dependent connections between gate lines, leading to signal delay and installation issues in thin film transistor array substrates.
Innovation Solution
A gate driver design that shares clock signals among multiple stages to output sensing, reference, and scan signals, reducing the area and load of the gate driver, and incorporating a controller to manage these signals effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate lines are dependently connected to divide scan signals in the display panel, then scan signals can be properly distributed to pixels, but the load in the gate driver is increased and output signal is delayed
Solution Approach 1:
The gate driver is divided into multiple independently operable stages (first stage and second stage), where each stage can generate and output scan signals separately. This segmentation allows the driver to distribute scan signals through multiple independent paths rather than through a single overloaded dependent connection system, reducing the load on each individual path while maintaining proper signal distribution to all pixels.
2Reliability
If gate lines are dependently connected to divide scan signals, then scan signals can be distributed to pixels, but the size of the gate driver is increased making installation difficult
Solution Approach 1:
The gate driver is segmented into two independent stages that can be implemented as separate circuit blocks. This allows for a more compact layout where each stage uses its own dedicated transistors and control signals, reducing the overall area required compared to a single large dependent connection system. The independent stages can be arranged efficiently on the TFT array substrate.
Solution Approach 2:
The patent utilizes the spatial arrangement of gate lines in the display panel by applying scan signals from different stages to different sets of gate lines (odd-numbered and even-numbered lines). This dimensional organization allows the gate driver to serve the entire display panel through coordinated operation of compact stages, reducing the physical footprint of the driver circuit.
3Ease of operation
If multiple clock signals are used for different output units, then each signal can be controlled independently, but the area of the gate driver is increased
Solution Approach 1:
A single clock signal is designed to serve multiple functions by being applied to different output units (first and second output units) that generate different scan signals. This multi-functional clock signal approach allows independent control of multiple scan signal outputs without requiring separate clock signals for each, thereby reducing the overall area of the gate driver while maintaining operational independence through phase and timing control.
Data Source
AI summary
According to an aspect of the present disclosure, a gate driver includes a plurality of stages which is dependently connected to each other and each of the plurality of pixels includes: a first output unit which outputs a sensing signal by voltages of a Q node and a QB node; a second output unit which outputs a reference signal by the voltages of the Q node and the QB node; a third output unit which outputs a scan signal by the voltages of the Q node and the QB node; a first controller which controls the Q node; and a second controller which controls the QB node, and at least two of the first to third output units share at least one clock signal among a plurality of clock signals, thereby reducing an area of the gate driver.