Gate Driver Clock-Level Shifting for Lower Display Power
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Solution Overview
Problem
The power consumption of gate drivers in display devices increases due to high amplitude clock signals applied to buffer transistors, which affects the efficiency and reliability of the display panel.
Innovation Solution
A gate driver design that utilizes transistors and capacitors to manage clock signals with varying phases and voltage levels, including a first transistor for transmitting an input signal to a control node and a seventh transistor for outputting a clock signal with a higher voltage level, reducing the amplitude of the clock signals and thereby lowering power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high amplitude clock signal is applied to the buffer transistor to ensure proper signal transmission, then the gate signal can be reliably output, but the power consumption of the gate driver increases
Solution Approach 1:
The gate driver is divided into multiple stages: a first clock signal generation unit that generates a clock signal with a first low gate voltage level, and a second clock signal generation unit that generates a clock signal with a second low gate voltage level higher than the first. This segmentation allows different parts of the circuit to operate at optimized voltage levels, reducing overall power consumption while maintaining reliable signal transmission through proper staging of the buffer transistors.
Solution Approach 2:
The invention changes the voltage level parameter of the clock signal by introducing a second low gate voltage level that is higher than the first low gate voltage level. By adjusting this voltage parameter in the second clock signal generation unit, the amplitude of the clock signal is reduced, which directly lowers the power consumption of the buffer transistor while still ensuring adequate signal transmission reliability through the staged architecture.
2Use of energy by moving object
If the amplitude of the clock signal is reduced to lower power consumption, then energy efficiency improves, but the ability to drive the buffer transistor effectively may be compromised
Solution Approach 1:
The circuit dynamically switches between different clock signal paths depending on the operational phase. During certain phases, the first clock signal with the lower voltage level is used to reduce power consumption, while during other phases, the second clock signal with the higher voltage level is used to ensure adequate driving capability. This dynamic switching allows the system to optimize between power consumption and driving capability based on real-time operational requirements.
Solution Approach 2:
The second clock signal generation unit acts as an intermediary between the first clock signal generation unit and the buffer transistor. It receives the first clock signal, transforms it into a second clock signal with a higher low gate voltage level, and then applies this transformed signal to the buffer transistor. This intermediary transformation ensures that the buffer transistor receives an appropriately leveled signal that maintains driving capability while reducing the overall amplitude and power consumption.
Data Source
AI summary
A gate driver includes a first transistor configured to transmit an input signal to a control node in response to a first clock signal swinging between a first low gate voltage and a high gate voltage, a sixth transistor configured to output the high gate voltage as a gate signal to an output terminal in response to a signal of an inverting control node, and a seventh transistor configured to output a second clock signal swinging between a second low gate voltage, which has a level that is higher than a level of the first low gate voltage, and the high gate voltage as the gate signal to the output terminal in response to a signal of the control node.