Gate Driver Reducing Clock Signals for Power Savings
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Solution Overview
Problem
High power consumption in gate driver on array (GOA) circuits due to multiple clock signals, especially in large-size high-definition displays, which increases costs and reduces competitiveness.
Innovation Solution
A gate driver design utilizing two inversed clock signals and an intermediate signal to control the charging and discharging periods, reducing the number of clock signals required for outputting gate driving signals, thereby minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple clock signals (6 or 8) are used in GOA circuits for large-size high-definition displays, then the reliability and functionality of the gate driver is improved, but the power consumption increases significantly
Solution Approach 1:
The patent combines multiple clock signal functions into fewer clock signals by using different phase combinations and timing strategies. Specifically, it uses 5 clock signals (CK1-CK5) to replace the conventional 6-8 clock signals by merging their functions through careful phase arrangement and shared signal paths, thereby reducing power consumption while maintaining reliability
Solution Approach 2:
The patent employs periodic action by using phase-shifted clock signals where CK3 is inverted relative to CK1, and CK4-CK5 are phase-shifted versions of CK2. This periodic phase modulation allows the same clock signal to serve multiple functions at different time intervals, reducing the total number of clock signals needed while maintaining the required timing for reliable operation
2Adaptability or versatility
If the number of clock signals is increased from 4 to 6 or 8 for high-definition panels, then the gate driving capability is improved, but the power consumption becomes significant
Solution Approach 1:
The patent changes the parameters of existing clock signals by introducing phase shifts and inversions. Specifically, CK3 is inverted relative to CK1, and CK4-CK5 are phase-shifted versions of CK2, allowing the same frequency clock signals to provide different timing functions. This parameter modification enables reduced clock signal count while maintaining enhanced gate driving capability
3Reliability
If more clock signals are used to ensure reliability in large-size displays, then the reliability is improved, but the cost of the driving circuit increases
Solution Approach 1:
The patent merges the functions of 6-8 clock signals into 5 clock signals by combining their roles through phase modulation and shared signal paths. This reduction in clock signal count directly simplifies the driving circuit complexity and reduces associated costs while maintaining the reliability required for large-size display applications
Data Source
AI summary
The present invention proposes a gate driver including a plurality of gate driver on array (GOA) units. Each of the GOA unit includes a main driving circuit, a starting signal output circuit, and a plurality of gate driving circuits. The gate driver utilizes a starting signal and two inversed clock signals to control the charging period and the discharging period of the gate driver. Furthermore, the gate driver utilizes multiple clock signals to control the output of the gate driving signals. In this way, the number of the clock signals is reduced and thus the power consumption is also reduced.