Display Gate Driver Clock Swing Reduction for Lower Power
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Solution Overview
Problem
The power consumption of gate drivers in display devices increases due to high amplitude clock signals applied to buffer transistors, which affects the efficiency and reliability of the display device.
Innovation Solution
A gate driver design that utilizes transistors and capacitors to manage clock signals with varying phases and voltages, including a first clock signal with a high gate voltage and a second clock signal with a lower gate voltage, reducing the amplitude of the second clock signal, and includes a phase difference and capacitor design to reduce power consumption, utilizing a phase difference, and capacitors to reduce the power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the amplitude of the clock signal applied to the buffer transistor is increased, then the gate driver can drive the display panel more effectively, but the power consumption of the gate driver increases
Solution Approach 1:
The patent divides the clock signal generation into two separate clock signals with different voltage levels and phases. The first clock signal has a high voltage level for effective switching, while the second clock signal has a lower voltage level applied to the buffer transistor, reducing power consumption while maintaining driving capability through phase differentiation.
Solution Approach 2:
The patent changes the voltage level parameter of the clock signal by generating a second clock signal with a lower voltage level than the first clock signal. This parameter change allows the buffer transistor to operate with reduced voltage swing, thereby reducing power consumption while still achieving effective gate signal output through the phase difference between the two clock signals.
2Power
If a single high-amplitude clock signal is used for the buffer transistor, then the gate signal output is strong, but the power consumption increases
Solution Approach 1:
The patent introduces dynamic phase control between the first and second clock signals. The phase difference between these clock signals is dynamically adjusted to optimize the gate signal output timing and strength, allowing the buffer transistor to achieve strong output capability while operating with lower voltage amplitude, thus reducing power consumption.
Solution Approach 2:
The patent uses the phase relationship between the first and second clock signals as an intermediary mechanism. By controlling the phase difference, the system achieves effective gate signal output without requiring high voltage amplitude on the buffer transistor, thereby decoupling output strength from power consumption.
Data Source
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AI summary
A gate driver (10-12, 121-124) includes a first transistor (T1) configured to transmit an input signal (INS) to a control node (Q) in response to a first clock signal (CLK1) swinging between a first low gate voltage (VGL1) and a high gate voltage (VGH), a sixth transistor (T6) configured to output the high gate voltage (VGH) as a gate signal (GS) to an output terminal (TOUT) in response to a signal of an inverting control node (QB), and a seventh transistor (T7) configured to output a second clock signal (CLK2) swinging between a second low gate voltage (VGL2), which has a level that is higher than a level of the first low gate voltage (VGL1), and the high gate voltage (VGH) as the gate signal (GS) to the output terminal (TOUT) in response to a signal of the control node (Q).