Gate Driver Clock Timing for High-Rate Scan Ripple Reduction
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Solution Overview
Problem
In high scan rate mode, the magnitude of ripple occurring in the control node of a gate driver increases significantly compared to the normal scan rate mode, which affects the stability and image quality of display devices.
Innovation Solution
A gate driver design that includes a level shifter to output different modes of gate clocks and a gate shift register to synchronize scan signals, with specific delay differences between adjacent gate clocks, reducing ripple magnitude to normal scan rate levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate driver operates in high scan rate mode with gate clock pair having the same phase, then the scan rate is improved, but the magnitude of ripple in the control node increases by about two times
Solution Approach 1:
The patent introduces asymmetric delay timing between the first and second gate clocks in the high scan rate mode. Specifically, the first gate clock has a different delay time than the second gate clock, creating an asymmetric clocking scheme that prevents simultaneous switching of adjacent gate lines. This asymmetry distributes the ripple effects over time rather than having them occur simultaneously, thereby reducing the peak ripple magnitude in the control node while maintaining the high scan rate operation.
2Loss of time
If scan signals are supplied to adjacent gate lines simultaneously in high scan rate mode, then the frame time is reduced by half, but the ripple magnitude increases significantly
Solution Approach 1:
The patent implements a periodic action principle by introducing alternating delay patterns for different gate clocks. In the high scan rate mode, the gate clocks are configured with alternating delay times (first gate clock has delay time T1, second gate clock has delay time T2, where T1 ≠ T2). This periodic variation in delay timing ensures that adjacent gate lines are scanned in a staggered periodic fashion, reducing simultaneous ripple generation while maintaining the accelerated scan rate that halves the frame time.
Data Source
AI summary
A gate driver includes a level shifter configured to output first-mode gate clocks in a normal scan rate mode and output second-mode gate clocks in a high scan rate mode and a gate shifter register configured to output normal scan rate scan signals synchronized with the first-mode gate clocks in the normal scan rate mode and output high scan rate scan signals synchronized with the second-mode gate clocks in the high scan rate mode. Adjacent gate clocks of the first-mode gate clocks have a delay difference equal to one horizontal period, and the second-mode gate clocks include first to fourth gate clocks where a phase is sequentially shifted. The first and third gate clocks have a delay difference equal to the one horizontal period, the first and second gate clocks have a delay difference equal to a time which is less than the one horizontal period, and the third and fourth gate clocks have a delay difference equal to a time which is less than the one horizontal period.