Gate Driver Clock Wiring Capacitance Compensation
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Solution Overview
Problem
In liquid crystal display (LCD) devices, the difference in capacitance between clock wires connected to each stage of the gate driver leads to varying clock signal delays, resulting in inconsistent gate signal outputs, which affects display quality.
Innovation Solution
The design includes a common electrode with openings of varying sizes to reduce capacitance differences between clock wiring connection portions and stages, and additional resistors are used to compensate for resistance differences between connection lines, ensuring a constant gate signal output across all stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uniform clock wires and connection lines are used for all stages, then the device structure is simple, but capacitance differences cause varying clock signal delays and inconsistent gate signal outputs
Solution Approach 1:
The patent applies local quality by creating openings in the common electrode with different sizes at different locations. Specifically, openings closer to the gate driver are larger while those farther away are smaller, compensating for the increased capacitance and signal delay in longer connection lines. This localized variation in opening size ensures uniform clock signal delivery across all stages without requiring completely different wiring structures.
2Reliability
If connection lines are made longer to reach distant stages, then all stages can be connected, but resistance differences cause timing shifts in gate signal output
Solution Approach 1:
The patent applies parameter changes by adjusting the opening size parameter in the common electrode to compensate for varying connection line characteristics. By changing the opening size based on distance from the gate driver, the effective capacitance is adjusted to compensate for longer connection lines, thereby maintaining consistent timing across all stages without adding complex resistance compensation circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces clock signal delay and maintains a constant gate signal output at every stage, improving display quality by minimizing timing shifts during pixel charging.
Implementation Method 1
the difference in capacitance generated by different clock wires connected to each stage
Data Source
AI summary
A display device includes: a first substrate including a gate driver disposed in a non-display area; and a second substrate including a common electrode disposed apart from the first substrate, the gate driver includes: first and second clock wires configured to supply first and second clock signals, respectively; first and second stages configured to receive the first and second clock signals, respectively; a first connection line connecting the first clock wire and the first stage; a second connection line connecting the second clock wire and the second stage; a first contact portion connecting the first clock wire and the first connection line; and a second contact portion connecting the second clock wire and the second connection line. The common electrode includes: first and second openings corresponding to the first and second contact portions, respectively. The first opening and the second opening have different sizes in a plan view.