Gate Driver Common Mode Choke for Stable Parallel Power Modules
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Solution Overview
Problem
Paralleled power semiconductor modules often experience asymmetries in loading and gate signal stabilization due to non-ideal characteristics and layout asymmetries, leading to increased costs and potential violations of safe operating areas, with existing solutions like derating and common/differential mode chokes facing challenges in design complexity and resonance issues.
Innovation Solution
A power semiconductor unit with a common mode coupling device placed before the gate driver circuit, utilizing a common mode choke with a single core to provide high impedance for common mode currents, which improves current sharing dynamics and reduces switching losses, allowing for more symmetric sharing of switching losses among modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If common mode chokes are used between gate driver circuit and power semiconductor gate, then gate signal stabilization is achieved, but leakage inductance causes undesired resonances in gate path
Solution Approach 1:
The patent divides the common mode choke into two separate chokes: one placed in the gate path and another in the DC supply path. This segmentation allows each choke to be optimized independently - the gate path choke can use smaller inductance values to avoid resonances while still providing common mode filtering, and the DC supply choke handles the bulk of the common mode current suppression without affecting gate signal stability.
Solution Approach 2:
The patent introduces an intermediary approach by placing the common mode choke at the DC supply input of the gate driver rather than directly in the gate signal path. This intermediary position allows the choke to suppress common mode currents before they reach the sensitive gate circuitry, stabilizing gate signals without introducing problematic resonances in the high-frequency gate path.
2Reliability
If larger common mode inductance values are used, then common mode current suppression is improved, but leakage inductance impact on switching performance increases
Solution Approach 1:
The patent segments the common mode suppression function across two separate choke locations - one at the DC supply input and another at the gate output. This allows the DC supply choke to handle larger inductance values for effective common mode suppression, while the gate path choke uses smaller inductance to minimize impact on switching performance and avoid resonances.
Solution Approach 2:
The patent applies different inductance values and choke characteristics at different locations in the circuit. The DC supply path choke uses larger inductance optimized for suppressing common mode currents, while the gate path choke uses smaller inductance optimized for minimal impact on switching speed and performance. Each location has locally optimized choke parameters.
3Reliability
If derating is applied to paralleled power semiconductor modules, then non-idealities and asymmetries are compensated, but capacity utilization decreases
Solution Approach 1:
The patent introduces common mode chokes as intermediary elements that actively suppress common mode currents and reduce the impact of asymmetries and non-idealities in paralleled modules. This allows the system to operate at or near full capacity without requiring derating, as the chokes compensate for imbalances by filtering out the problematic common mode components that would otherwise limit reliable operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the impact of leakage inductance on switching performance, enables larger common mode inductance values, and minimizes component size, while ensuring stable gate signal operation and reduced risks of overvoltages, enabling efficient paralleling of power semiconductor units.
Implementation Method 1
a common mode coupling device 20 placed before a gate driver circuit 18 for switching a gate voltage supplied to a power semiconductor switch 14
Data Source
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AI summary
A power semiconductor unit (12) comprises a power semiconductor switch (14) adapted for switching a current through the power semiconductor unit (12), the power semiconductor switch comprising a positive power input (16a), a negative power input (16b) and a gate (38); a gate driver circuit (18) for receiving a gate signal (VS) from a gate signal input (28) and for connecting the gate (38) of the power semiconductor switch (14) with a positive voltage reference (+VG) from a positive voltage input (26); and a common mode coupling device (20, 20') for providing an impedance for a common mode current through auxiliary inputs of the power semiconductor unit (12), the auxiliary inputs comprising the gate signal input (28), the positive voltage input (26), a positive power reference input (58) connected with the positive power input (16a) and a negative power reference input (30) connected with the negative power input (16b); wherein the common mode coupling device (20, 20') comprises a common mode choke with a core (36) coupling the auxiliary inputs (26, 28, 30, 32, 58).