Gate Driver Circuit Area Reduction via Common Control Nodes
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Solution Overview
Problem
Existing display devices have a significant area dedicated to the gate driver, which can lead to increased dead space and reduced efficiency.
Innovation Solution
The proposed solution involves a gate driver design with a reduced area, achieved by incorporating a common circuit that controls voltages for control nodes and an individual circuit that outputs scan signals. This design includes scan buffer transistors and a scan hold transistor to maintain scan signals at a low voltage, thereby reducing the overall area of the gate driver.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional gate driver design is used, then the gate driver can generate gate signals for multiple pixels, but the area occupied by the gate driver becomes large
Solution Approach 1:
The gate driver is divided into multiple independent stages, where each stage generates gate signals for a specific subset of pixels. This segmentation allows the overall gate driver to handle more pixels while keeping each individual stage compact, thus reducing the total area required.
Solution Approach 2:
Each stage in the gate driver is designed to perform multiple functions: generating scan signals, generating gate signals, and controlling pixel activation. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby minimizing the overall gate driver area.
2Area of stationary object
If the gate driver area is reduced, then dead space in the display device is minimized, but the complexity of the gate driver circuit increases
Solution Approach 1:
Multiple functions are merged into unified circuit blocks. For example, the scan signal generation and gate signal generation functions are combined within each stage, sharing common components like transistors and control nodes. This merging reduces the overall area while managing complexity through functional integration.
Solution Approach 2:
The gate driver employs dynamic control mechanisms where control nodes are activated only when needed. The use of enable signals and dynamic switching allows the circuit to operate efficiently with fewer active components at any given time, reducing the perceived complexity while maintaining compact size.
Data Source
AI summary
A gate driver includes a plurality of stages. Each of the plurality of stages includes a common circuit which controls a voltage of a first control node, a voltage of a second control node, and a voltage of an inverted control node, and an individual circuit which outputs a plurality of scan signals in response to the voltage of the first control node and the voltage of the inverted control node. The individual circuit includes a plurality of scan buffer transistors which output a plurality of scan clock signals as the plurality of scan signals in response to the voltage of the first control node, and a scan hold transistor which maintains the plurality of scan signals at a first low voltage in response to the voltage of the inverted control node.