Gate Driver Compensation for Long Clock Line Voltage Stability
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Solution Overview
Problem
In OLED display devices, the voltage of clock signals supplied to stages far from the printed circuit board is affected by load changes due to increased resistance and parasitic capacitance in the clock line, leading to defects in gate pulse output.
Innovation Solution
A gate driver with stages cascade-connected through a carry signal line, including a compensation mechanism that applies a compensation gate-on voltage when the gate-on voltage of a clock signal differs, using transistors to maintain stable gate-source voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the clock line length is increased to supply clock signals to stages far from the printed circuit board, then the coverage area is improved, but the voltage stability deteriorates due to increased resistance and parasitic capacitance
Solution Approach 1:
The patent introduces a compensation circuit as an intermediary between the clock signal source and the distant stages. This compensation circuit detects voltage drops caused by resistance and parasitic capacitance in the extended clock line and applies compensating voltages to maintain stable operation, effectively mediating the harmful effects of the long clock line.
Solution Approach 2:
The patent dynamically adjusts voltage parameters (gate-on voltage and gate-off voltage levels) based on the detected clock signal voltage. By changing these voltage parameters in response to line conditions, the system compensates for the deteriorating voltage stability caused by the extended clock line length.
2Area of stationary object
If the clock line resistance and parasitic capacitance are increased due to extended length, then the coverage area is improved, but the signal transmission reliability deteriorates
Solution Approach 1:
The patent implements a feedback mechanism where the voltage of the clock signal is continuously monitored, and based on this feedback, compensation voltages are applied to maintain reliable signal transmission. The compensation circuit uses the detected voltage levels to adjust the gate-on and gate-off voltages, ensuring that stages far from the printed circuit board receive reliable clock signals despite the degraded transmission conditions.
3Reliability
If the gate-on voltage level is changed to compensate for voltage drops, then the signal transmission reliability is improved, but the device complexity increases due to additional compensation circuits
Solution Approach 1:
The patent designs the compensation circuit to perform multiple functions: it detects clock signal voltage levels, determines appropriate compensation amounts, and adjusts both gate-on and gate-off voltages. This multi-functional approach consolidates what could be multiple separate circuits into a single integrated compensation unit, reducing overall device complexity while maintaining reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents driving failures by stabilizing gate pulse output across the display panel, ensuring consistent signal transmission despite load variations.
Implementation Method 1
a voltage of the clock supplied to the stage disposed far from the printed circuit board may be changed by the influence of a load connected to the stage due to an increase in length of a clock line. As the length of the clock line increases, the clock signal having a constant voltage may not be supplied due to the load caused by the resistance of the clock line
Implementation Method 2
As the length of the clock line increases, the clock signal having a constant voltage may not be supplied due to the load caused by the resistance of the clock line and a parasitic capacitor connected to the clock line
Data Source
AI summary
The present specification discloses a gate driver, a display device including the same, and a method of driving the display device. When a gate-on voltage of a Jth clock signal differs from a gate-on voltage of the first clock signal, the gate driver applies a compensation gate-on voltage that is a gate-on voltage at a changed voltage level to a gate-on voltage node. The display device includes a sensing unit for sensing a clock signal, and a compensation unit for applying the compensation gate-on voltage to the gate driver from the sensed clock signal. According to the present specification, a gate-source voltage of a transistor disposed on an output unit may be maintained at a previous voltage. In addition, it is possible to prevent driving failures caused by a load received by the clock signal supplied to a stage disposed relatively far away.