Gate Driver Circuit for DC-DC Converters with Dynamic Drive Strength
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Solution Overview
Problem
Switched mode power supplies (SMPS) experience ringing due to parasitic inductances, leading to electromagnetic interference and potential component damage, as rapidly changing currents through power transistors excite resonant tanks, causing voltage transients and inefficiencies.
Innovation Solution
A gate driver circuit is implemented with control circuitry that identifies rising and falling current transitions to adjust gate drive strength, reducing the peak-to-peak voltage of ringing by tuning the gate drive during these transitions and increasing it outside of them to minimize switching losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If gate drive strength is increased to reduce switching losses, then efficiency is improved, but ringing voltage transients increase causing electromagnetic interference and potential component damage
Solution Approach 1:
The gate driver dynamically adjusts its drive strength based on the switching phase. During rising current transitions, it provides reduced drive strength to minimize ringing, while during falling current transitions or steady states, it increases drive strength to reduce switching losses. This dynamic adaptation resolves the contradiction by optimizing drive strength for different operational conditions rather than using a fixed high drive level throughout.
Solution Approach 2:
The invention changes the gate drive parameter (drive strength) based on the detected current transition state. By monitoring whether the current is rising or falling, the system adjusts the gate drive voltage or current magnitude accordingly, transforming a static parameter into a dynamic one that adapts to real-time conditions to simultaneously reduce both switching losses and ringing.
2Productivity
If switching speed is increased to improve productivity, then power conversion efficiency is improved, but electromagnetic interference from ringing increases
Solution Approach 1:
The gate driver applies different drive characteristics to different phases of the switching cycle. During rising current transitions, it uses a softer, more controlled drive to reduce ringing, while during other phases it uses stronger drive to maintain high switching speed and efficiency. This local differentiation of drive quality resolves the contradiction between speed and EMI.
Solution Approach 2:
The system detects rising current transitions in advance and proactively reduces gate drive strength before significant ringing can occur. This preliminary anti-action prevents the harmful electromagnetic interference from generating in the first place, while maintaining high efficiency during non-critical switching phases.
3Object-affected harmful factors
If gate drive strength is reduced to limit ringing, then electromagnetic interference is reduced, but switching losses increase reducing efficiency
Solution Approach 1:
The gate driver periodically alternates between high drive strength and reduced drive strength based on the switching cycle phase. During falling current transitions and steady states, it applies high drive strength to minimize losses, while during rising current transitions it reduces drive strength to limit ringing. This periodic modulation of drive strength resolves the contradiction by applying the appropriate drive level at the appropriate time.
Solution Approach 2:
The system dynamically switches between two drive strength modes based on real-time detection of current transition direction. This dynamic adjustment ensures that the gate drive strength is optimized for each phase of operation, achieving both EMI reduction and efficiency maintenance without the trade-offs of static drive levels.
Data Source
AI summary
A device includes a first FET coupled between first and drive terminals, and is configured to turn on/off responsive to a PWM signal having a first/second state, respectively. A second FET is coupled between the first and drive terminals and is configured to turn on responsive to the PWM signal having the first state, and turn off responsive to expiration of a particular delay after the second FET turns on. A third FET is coupled between drive and second terminals, and is configured to turn on/off responsive to the PWM signal having the second/first state, respectively. A fourth FET is coupled between the drive and second terminals, and is configured to turn on responsive to the PWM signal having the second state if a switching terminal has a first voltage, and turn off responsive to the PWM signal having the first state or the switching terminal having a second voltage.