High-Voltage Gate Driver With Shared Dead-Time Generation
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Solution Overview
Problem
High voltage drive ICs face mismatching of dead time in high side and low side gate drive signals due to different signal paths for generating dead time, leading to errors and instability in output signals.
Innovation Solution
A high voltage drive circuit with an edge detector generating edge detection signals for both high side and low side inputs, a dead time generator using a delay capacitor and comparator to produce a dead time signal, and a drive signal generator inserting this dead time into the signals to minimize mismatching and ensure stable output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate signal paths are used for generating dead time in high side and low side gate drive signals, then the driver can independently control each side, but dead time mismatching occurs leading to output signal errors
Solution Approach 1:
The patent merges the separate dead time generation paths into a single shared signal path. The edge detector and dead time generator are commonly shared between high side and low side gate drive signals, ensuring that both sides receive identical dead time insertion based on the same reference edge detection, thereby eliminating dead time mismatching while maintaining independent control through separate output stages.
2Ease of manufacture
If different signal paths are used for high side and low side gate drive, then each side can be optimized independently, but mismatching of dead time is generated
Solution Approach 1:
The patent combines the critical dead time generation functions into shared circuitry. The edge detector detects edges from both high side and low side inputs and generates a common dead time signal that is inserted into both output paths, ensuring consistent dead time insertion and eliminating mismatching that would compromise output signal stability.
Solution Approach 2:
The patent segments the driver circuit into three functional modules: a commonly shared edge detector and dead time generator, separate delay circuits for high side and low side, and independent output stages. This segmentation allows independent optimization of each side's drive characteristics while maintaining synchronized dead time through the shared generation path.
3Adaptability or versatility
If dead time is generated separately for high side and low side, then customization is easier, but error in dead time increases
Solution Approach 1:
The patent merges the dead time generation mechanism into a single shared path that uses a common edge detection reference. The delay capacitor and comparator-based dead time generator produce a unified dead time signal that is applied to both high side and low side outputs, eliminating accumulation of timing errors that would occur with separate generation paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces dead time mismatching and ensures stable output signals by generating a dead time signal with minimal error, preventing shoot-through phenomena and maintaining system reliability.
Implementation Method 1
The dead time generator may include a delay capacitor charged in response to the edge detection signal
Implementation Method 2
a comparator for providing the dead time signal by comparing a delay voltage corresponding to an amount of electric charges changed in the delay capacitor with a reference voltage
Data Source
AI summary
A high voltage drive circuit includes an edge detector for generating an edge detection signal by detecting edges of a first high side input signal and a first low side input signal, the edge detector providing a high side delay signal and a low side delay signal by delaying the first high side input signal and the first low side input signal, a dead time generator for generating a dead time signal indicating a preset dead time in response to the edge detection signal, and a driver comprising a drive signal generator for providing a high side output signal and a low side output signal by inserting the preset dead time based on the dead time signal into the high side delay signal and the low side delay signal.