Gate Driver Delay Compensation for Display Pixel Charging
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Solution Overview
Problem
Display devices face image quality issues due to gate signal delay caused by wire resistance, leading to synchronization deviation with data voltage and inadequate charging of pixels, resulting in poor gray scale emission and image quality.
Innovation Solution
A display device and driving method that involve a gate driver delaying and advancing gate signals applied to gate lines within a frame, adjusting the time period for gate-on voltage application based on a reference data delay value to optimize the output enable margin between gate signals and data voltages, ensuring sufficient charging of pixels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate signals are applied to gate lines without delay compensation, then the circuit operation is simple, but the gate signal delay due to wire resistance causes synchronization deviation with data voltage and inadequate pixel charging
Solution Approach 1:
The gate driver performs preliminary delay compensation on gate signals before they are applied to gate lines. By calculating the wire resistance-induced delay in advance and pre-delaying the gate signals accordingly, the synchronization between gate signals and data voltages is maintained, ensuring accurate pixel charging without requiring complex real-time adjustment mechanisms.
Solution Approach 2:
Different gate signals are delayed by different amounts based on their specific wire resistance characteristics. The gate driver applies local delay compensation to each gate line according to its individual delay properties, rather than using a uniform delay for all lines. This targeted approach maintains synchronization accuracy while minimizing unnecessary complexity.
2Manufacturing precision
If the time period for gate-on voltage application is not adjusted, then the control circuitry is simple, but the output enable margin between gate signals and data voltages is suboptimal, resulting in poor image quality
Solution Approach 1:
The gate driver dynamically adjusts the time period parameter for gate-on voltage application based on the delay characteristics of each gate line. By changing this temporal parameter in response to measured or calculated wire resistance effects, the output enable margin between gate signals and data voltages is optimized, ensuring sufficient pixel charging time and improving image quality.
Solution Approach 2:
The gate driver incorporates feedback mechanisms to monitor the actual delay experienced by gate signals and adjusts the gate-on voltage time period accordingly. This closed-loop control ensures that the output enable margin is maintained at optimal levels despite variations in wire resistance, thereby consistent image quality.
3Reliability
If gate signals are delayed to compensate for wire resistance, then the synchronization with data voltage is improved, but the gate signal delay varies across different gate lines causing unequal charging times
Solution Approach 1:
The gate driver applies differentiated delay compensation to each gate line based on its specific wire resistance characteristics. By tailoring the delay amount to the local properties of each gate line, the system achieves synchronization accuracy for each individual line while maintaining consistent charging times across all lines, as each line receives the precise delay it needs.
Solution Approach 2:
The system performs preliminary characterization of wire resistance for each gate line and pre-configures appropriate delay values before operation. This advance preparation ensures that when gate signals are applied, each line experiences the correct delay compensation, achieving both synchronization accuracy and charging time consistency without requiring complex real-time adjustments.
Data Source
AI summary
A display device includes a display unit including a plurality of pixels, a plurality of gate lines and a plurality of data lines which are connected to the plurality of pixels, a data driver applying data voltages to the plurality of data lines, and a gate driver delaying and outputting first gate signals applied to gate lines among the plurality of gate lines in a first sub-frame included in one frame and advancing and outputting second gate signals which are applied to remaining gate lines among the plurality of gate lines in a second sub-frame.