Gate Driver Diode Clamping for Oxide TFT Ripple Discharge
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Solution Overview
Problem
The degradation of oxide TFTs in gate driver circuits leads to threshold voltage shifts and image quality degradation due to the inability to recover from DC gate bias stress, resulting in ripple voltages and improper discharge of gate lines.
Innovation Solution
Incorporating diodes between the clock input and output terminals of the gate driver stages, which are diode-connected transistors, to effectively discharge ripple voltages and prevent multi-output phenomena by turning on when the output voltage exceeds the clock input voltage by a threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If oxide TFTs are used in gate driver circuits, then high performance and high resolution are achieved, but threshold voltage shifts occur due to DC gate bias stress and the degradation cannot be recovered
Solution Approach 1:
The patent applies periodic AC voltage to the QB node instead of continuous DC voltage. This periodic action causes the pull-down transistor to alternately conduct and cut off, enabling the Q node to be periodically charged and discharged. This periodic operation prevents cumulative DC gate bias stress on the oxide TFT, avoiding threshold voltage shifts and maintaining long-term operational stability.
2Power
If the Q node is pre-charged by gate-on voltage VGH and shift clock CLK is input, then the output terminal is charged to VGH, but when the Q node is floated, the Q node voltage is raised to 2VGH by bootstrapping causing excessive voltage
Solution Approach 1:
The patent introduces a diode as an intermediary component between the Q node and the output terminal. This diode acts as a voltage clamp that allows the output terminal to be charged to VGH normally, but prevents the voltage from exceeding VGH + Vth (diode threshold voltage) during bootstrapping. The diode conducts when the voltage exceeds this limit, dissipating excess energy and protecting the transistor from excessive voltage stress.
3Power
If the pull-down transistor discharges the output terminal using gate-off voltage VGL, then the output voltage is lowered to VGL, but degradation of oxide TFT makes discharge ineffective causing ripple voltage
Solution Approach 1:
The patent uses periodic AC voltage on the QB node to make the pull-down transistor conduct alternately, creating multiple discharge opportunities. Instead of relying on a single discharge event that may be insufficient due to TFT degradation, the periodic conduction allows the capacitor to be discharged in multiple small steps, effectively removing ripple voltage even when the transistor has degraded.
Solution Approach 2:
The patent maintains continuous discharge action through periodic QB node voltage application. Rather than having discrete, infrequent discharge events, the pull-down transistor is kept in a state of continuous periodic operation, ensuring that ripple voltage is continuously suppressed throughout the operating period, which is essential for maintaining stable output despite TFT degradation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces ripple voltages and maintains stable output voltages, improving image quality by ensuring proper discharge of gate lines and reducing TFT degradation.
Implementation Method 1
a first diode connected between the clock input and the first output terminal... When a voltage of the first output terminal is higher than a voltage of the clock input by at least a threshold voltage of the first diode, the first diode may be turned on and the voltage of the first output terminal may be discharged through the clock input
Implementation Method 2
the Q node voltage floated is raised to 2VGH by bootstrapping through a capacitance between the drain and a gate of the pull-up transistor Tu
Data Source
AI summary
A gate driver and a display device using the same are disclosed. The gate driver includes a plurality of stages connected in a cascade connection manner, and each of the stages include a clock input configured to receive a shift clock signal, a first output terminal, and a second output terminal. Each of the stages generates a first output voltage that is transmitted to another stage through the first output terminal and a second output voltage that is supplied to a gate line of a display panel through the second output terminal. Each of the stages includes a first diode connected between the clock input and the first output terminal.