Gate Driver Circuit Integration in Display Panel Bezel Reduction
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Solution Overview
Problem
Existing display devices face challenges in minimizing bezel area, achieving high resolution and large area displays, and reducing the interval between signal and power lines, which affects design ease and display quality.
Innovation Solution
The display device incorporates a display panel with a gate driver circuit disposed within the panel, utilizing a gate in array (GIA) manner to overlap the gate area with the active area, and includes a shielding pattern to improve display quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the gate driver circuit is disposed outside the active area (gate in panel manner), then the design is simpler, but the bezel area is larger and gate signal delay increases
Solution Approach 1:
The gate driver circuit is merged with the pixel circuit layer by disposing the gate area to overlap with the active area, integrating previously separate functional regions into a unified structure that reduces bezel area while maintaining design feasibility
Solution Approach 2:
The gate driver circuit is transitioned from a planar arrangement outside the active area to a three-dimensional overlapping configuration where the gate area extends into the active area vertically, utilizing the depth dimension to reduce frontal bezel area
2Ease of manufacture
If the gate driver circuit is disposed outside the active area, then manufacturing is easier, but gate signal delay increases and luminance uniformity deteriorates
Solution Approach 1:
The gate area is preliminarily configured to overlap with the active area during the manufacturing process, establishing the optimal signal transmission path before subsequent processing steps, which reduces gate signal delay while maintaining manufacturing feasibility
Solution Approach 2:
The overlapping region between the gate area and active area is locally optimized with specific structural characteristics that facilitate faster signal transmission and improved luminance uniformity while maintaining overall manufacturing simplicity
3Ease of operation
If signal lines and power lines are disposed with large intervals, then design is easier, but display quality deteriorates
Solution Approach 1:
The wiring structure is segmented into multiple layers with signal lines and power lines alternately disposed, allowing reduced horizontal intervals while maintaining vertical separation that simplifies design and improves display quality simultaneously
Solution Approach 2:
The line arrangement transitions from a two-dimensional planar layout to a three-dimensional multi-layer configuration, enabling closer spacing of signal and power lines while maintaining design ease through vertical stacking
Data Source
AI summary
A display device may include a display panel including a plurality of pixels; and a data driver circuit configured to supply a data signal to the plurality of the pixels through data lines. A gate driver circuit, configured to supply a gate signal to the plurality of the pixels through gate lines, is disposed in the display panel. The display panel includes a driving layer including a gate area having the gate driver circuit; and a pixel circuit layer including an active area having a pixel area in which each of the plurality of pixels is disposed and a non-active area around the active area. The pixel circuit layer includes a light emitting diode, a clock line configured to supply a clock signal to the gate driver circuit, and a shielding pattern between the light emitting diode and the clock line.