Gate Driver Signal Deactivation for Display Panel Charging
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Solution Overview
Problem
As display panel sizes increase and driving frequencies rise, the charging time for subpixels to reach data voltage decreases, leading to inefficiencies in existing display driving methods, particularly in managing gate line activation and deactivation to prevent pixel decay and flickering.
Innovation Solution
A display apparatus with a gate driver that deactivates at least one gate signal in a P-th frame, grouping gate lines into sets and adjusting scanning times based on comparisons between image frames, allowing for optimized gate line activation and deactivation to maintain image quality and reduce data charging time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate lines are activated in every frame to maintain image quality, then pixel decay and flickering are prevented, but charging time for subpixels becomes insufficient when driving frequency increases
Solution Approach 1:
The patent segments gate lines into multiple groups and selectively activates only certain groups in each frame based on image content analysis. This segmentation allows the system to maintain image quality for static regions while reducing charging time requirements for dynamic regions, resolving the contradiction between reliability and time loss.
Solution Approach 2:
The patent dynamically adjusts the activation pattern of gate lines based on real-time image content analysis. By comparing current frame data with previous frames, the system determines which gate lines require activation and which can be deactivated, making the gate driving pattern adaptive rather than fixed. This dynamic approach optimizes charging time while maintaining image quality.
2Speed
If driving frequency is increased to improve display performance, then refresh rate improves, but charging time for subpixels decreases leading to insufficient voltage charging
Solution Approach 1:
The patent extracts and identifies static image regions that do not require frequent updates, then deactivates gate lines corresponding to these regions during certain frames. By taking out the unnecessary gate activations for static content, the system can operate at high refresh rates without requiring full charging cycles for all pixels, thus resolving the contradiction between speed and time loss.
Solution Approach 2:
The patent changes the driving parameters by selectively applying different gate signaling patterns to different gate line groups based on image content. This parameter change allows the system to maintain high overall refresh rates while providing extended charging time to specific regions that require it, resolving the contradiction between speed and charging time.
3Reliability
If all gate lines are scanned in every frame to ensure complete image rendering, then image completeness is maintained, but power consumption increases
Solution Approach 1:
The patent segments the display into multiple gate line groups and selectively scans only the necessary segments in each frame based on image content analysis. This segmentation maintains image completeness for dynamic regions while eliminating unnecessary power consumption in static regions, resolving the contradiction between reliability and energy use.
Solution Approach 2:
The system performs self-service by analyzing its own image content and autonomously determining which gate lines require activation. This self-adaptive mechanism ensures image completeness is maintained only where necessary, automatically reducing power consumption without external intervention, thus resolving the contradiction between reliability and energy use.
Data Source
Figure 1
Figure 2~3A
Figure 3B~3C
AI summary
A display apparatus includes a display panel (100) having a plurality of gate lines (GL), a plurality of data lines (DL), and a plurality of subpixels (SP). Each of the plurality of subpixels (SP) includes a subpixel electrode (SPE) connected to one of the plurality of gate lines (GL) and one of the plurality of data lines (DL) through a switching element (TR). A gate driver (300) is configured to output a plurality of gate signals (G1 to G9) to the plurality of gate lines (GL)and to deactivate at least one of the plurality of gate signals (G1 to G9) in a P-th frame. A data driver (500) is configured to output a plurality of data voltages to the plurality of data lines (DL). Here, P is a positive integer.