Gate Driver Integrated on Display Panel for Reduced Non-Display Area
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Solution Overview
Problem
The integration of a gate driver on a display panel faces issues such as temperature-dependent semiconductor characteristics, noise generation, and leakage currents due to ripple in the gate driver, leading to poor output characteristics and reliability, especially at high and low temperatures, and challenges in reducing the non-display area width.
Innovation Solution
A gate driver structure with multiple stages, including pull-up, pull-down, reset, and buffer node stabilizer transistors, is designed to reduce voltage differences between nodes, improve transistor output capacity, and apply different low voltages to enhance reliability and power consumption, while reducing the width of the gate driver.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gate driver is integrated on the display panel, then manufacturing cost is reduced, but temperature-dependent semiconductor characteristics cause noise generation and poor output characteristics
Solution Approach 1:
The gate driver is divided into multiple stages, with each stage independently driving a specific gate line. This segmentation isolates temperature-dependent variations to individual stages, preventing noise propagation across the entire display panel while maintaining the integration benefit.
Solution Approach 2:
Different voltage levels are applied to different stages of the gate driver based on their specific requirements. By adjusting voltage parameters for each stage, the circuit compensates for temperature-induced semiconductor characteristic changes, ensuring stable output characteristics across varying temperatures.
2Ease of manufacture
If the gate driver is integrated on the display panel, then manufacturing cost is reduced, but leakage current is generated due to ripple
Solution Approach 1:
Capacitors are strategically placed within the gate driver circuit to preemptively suppress voltage ripples before they can cause leakage current. This prior cushioning approach prevents harmful effects rather than correcting them after occurrence, maintaining low leakage current while keeping the driver integrated.
3Area of stationary object
If the width of non-display area is decreased, then display area is increased, but it becomes difficult to integrate the gate driver
Solution Approach 1:
The gate driver circuit is arranged in a multi-dimensional layout within the non-display area, utilizing vertical stacking and layered routing. This dimensional optimization allows the gate driver to fit into reduced non-display areas without excessive complexity, maintaining high display area while enabling integration.
4Reliability
If multiple transistors are added to stabilize buffer node voltage, then reliability is improved, but device complexity increases
Solution Approach 1:
The buffer node stabilizing function is merged with existing driver stage circuits by sharing transistors and capacitors across multiple functions. This combining approach provides voltage stabilization without proportionally increasing device complexity, as the same components serve both driving and stabilizing roles.
Data Source
AI summary
Provided is a gate driver including a plurality of stages respectively transferring gate-on voltages to a plurality of gate lines. The stage includes a pull-up driver including a first transistor, the first transistor having a control terminal connected to a first node, an output terminal connected to a output terminal of a present stage and an input terminal connected to a first clock terminal, a first node pull-down portion including a second transistor, the second transistor having an input terminal connected to a buffer node, an output terminal connected to the first node and a control terminal connected to a second node, and a buffer node stabilizer including a third transistor, the third transistor having an input terminal and a control terminal connected to the first node, and an output terminal connected to the buffer node.