Gate Driver Circuit Layout for Low-Distortion Display Signals
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Solution Overview
Problem
Display devices with active matrix mode suffer from signal delays and distortions due to parasitic capacitances and resistances in gate lines, especially as pixel quality and size increase, affecting image display quality.
Innovation Solution
The display device incorporates a first and second gate driver with flip flop circuits and transfer signal generation circuits that output signals with a half clock cycle delay, connected in a specific electrical configuration to reduce signal delays and distortions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the pixel portion is made high-quality with increased definition and size, then the display quality is improved, but signal delays and distortions increase due to parasitic capacitances and resistances in gate lines
Solution Approach 1:
The gate driver is divided into multiple gate drivers (first gate driver and second gate driver) that are provided at different locations (right side and left side) of the pixel portion. Each gate driver controls a specific set of gate lines, which segments the signal transmission paths and reduces the impact of parasitic capacitances and resistances on signal integrity while maintaining high display quality.
2Area of stationary object
If a single gate driver is provided close to one side of the pixel portion, then the circuit area is reduced, but the display portion becomes asymmetric and signal delays occur
Solution Approach 1:
The gate driver functionality is segmented into multiple gate drivers positioned at different sides of the pixel portion. This segmentation allows the circuit to maintain a compact area while achieving symmetric signal distribution, thereby improving signal integrity without excessive area increase.
Solution Approach 2:
Different gate drivers are positioned at specific locations (right side and left side) to locally optimize signal transmission to different regions of the pixel portion. This local quality approach ensures that each gate driver serves its nearby pixels with minimal signal degradation.
3Adaptability or versatility
If multiple shift registers are connected through gate lines, then the gate driver can control multiple pixels, but signal delays and distortions increase due to parasitic capacitances
Solution Approach 1:
The gate driver is segmented into multiple independent gate drivers, each with its own shift registers and control paths. This segmentation allows each gate driver to control a specific set of pixels through dedicated gate lines, maintaining control capability while reducing signal delays and distortions by limiting the length and parasitic effects of each signal path.
Data Source
AI summary
It is an object to provide a display device which can favorably display a image without delayed or distorted signals. The display device includes a first gate driver and a second gate driver. The first gate driver and the second gate driver each include a plurality of flip flop circuits and a plurality of transfer signal generation circuits. Both the flip flop circuit and the transfer signal generation circuit are circuits which output a signal inputted to a first input terminal with a half clock cycle delay. In addition, an output terminal of the transfer signal generation circuit is directly connected to a first input terminal of the flip flop circuit in the next stage. Therefore, delay and distortion of the signal which is inputted from the transfer signal generation circuit to the flip flop circuit can be reduced.