Gate Driver Dummy Output Buffer for Narrow Bezel Displays
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Solution Overview
Problem
Existing display devices face challenges in reducing the area occupied by gate drivers, which can lead to thicker bezels and potential image quality deterioration due to non-uniform gate signal output.
Innovation Solution
A gate driver configuration with multiple output buffers connected to a single shift register and a dummy output buffer at the last stage, allowing for efficient gate signal distribution to multiple gate lines and maintaining uniform image quality by synchronizing clock signals and using a dummy clock signal to prevent signal delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple shift registers are used to drive multiple gate lines, then gate signal output capability is improved, but gate driver area increases
Solution Approach 1:
The patent merges multiple shift register functions into a single shift register by connecting multiple output buffers to one shift register. This allows one shift register to drive multiple gate lines through the output buffers, reducing the number of shift registers needed and thereby reducing the gate driver area while maintaining the capability to drive multiple gate lines
2Area of stationary object
If output buffers are reduced to shrink area, then gate driver area is reduced, but gate signal output uniformity deteriorates
Solution Approach 1:
The dummy output buffer acts as an intermediary element that mediates between the shift register and the gate lines. It receives the clock signal and generates dummy gate signals that are applied to dummy gate lines, serving as a reference that ensures uniform timing and signal characteristics across all output buffers, thereby maintaining gate signal output uniformity
3Manufacturing precision
If dummy output buffer is added to maintain signal uniformity, then image quality is maintained, but device complexity increases
Solution Approach 1:
The dummy output buffer is a simplified copy of the actual output buffers. It replicates the essential function of receiving clock signals and generating timing references, but without the need to drive actual gate lines. This copying approach maintains signal uniformity and image quality while adding minimal complexity compared to full output buffers
Data Source
AI summary
A gate driver and a display device including the gate driver are discussed. The gate driver in one example includes a shift register configured to control charging and discharging of a Q node and a QB node, and i output buffers sequentially connected to the shift register, where i is a natural number of at least 2. Each output buffer is configured to output a gate signal to a corresponding gate line in response to a voltage of the Q node and a voltage of the QB node. The gate driver further includes a dummy output buffer connected to the last stage of the shift register and configured to output a dummy signal to a dummy line in response to the voltage of the Q node.