Gate Driver Dummy Clock Reduces Transistor Stress Voltage
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Solution Overview
Problem
In liquid crystal display (LCD) gate drivers, cumulative stress voltage accumulates in transistors due to the high-state voltage maintained for most of the frame period, leading to performance degradation and reduced lifespan.
Innovation Solution
Implementing a dummy clock during the vertical blank time to reduce stress voltage in shift registers by discharging the QB node to a lower power supply voltage, thereby minimizing cumulative stress voltage across transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the high-state voltage is maintained in shift registers for most of the frame period to enable continuous operation, then the productivity is improved, but the cumulative stress voltage accumulates in transistors leading to performance degradation
Solution Approach 1:
The patent applies periodic action by introducing a dummy clock signal that operates at a lower frequency than the main clock signals. This dummy clock periodically activates dummy shift registers during the frame period, creating rhythmic discharge cycles that prevent cumulative stress voltage accumulation while maintaining continuous operation of the main gate driver circuitry
Solution Approach 2:
The patent implements discarding and recovering by using dummy shift registers that temporarily hold and then discharge accumulated stress voltage. These dummy registers act as temporary storage elements that capture excess voltage stress during active periods and release it during dummy clock cycles, thereby recovering the health of the main transistors
2Duration of action of moving object
If the QB node is continuously held at high state to maintain shift register operation, then the gate driver can continuously scan gate lines, but the stress voltage accumulates reducing device lifespan
Solution Approach 1:
The patent applies preliminary action by proactively introducing dummy shift registers and dummy clock signals before the cumulative stress voltage reaches damaging levels. The dummy circuitry is pre-configured to periodically discharge the QB nodes of main shift registers, preventing stress accumulation before it causes transistor degradation or failure
Solution Approach 2:
The patent uses dummy shift registers as intermediary elements that mediate between the continuous operation requirement and the stress reduction need. These dummy registers act as buffer components that absorb and manage stress voltage, allowing the main shift registers to continue their gate scanning function without direct exposure to cumulative stress
Data Source
AI summary
A gate driver for a display device includes a plurality of shift registers to sequentially generate output signals during a frame period in response to multi-phase clocks; and a dummy clock provided to the plurality of shift registers during a vertical blank time to reduce a stress voltage in the shift registers, wherein an output of each of the shift registers is reset to a low state power supply voltage by an output signal of the next shift register.