Gate Driver Dummy Clock Line RC Load Reduction
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Solution Overview
Problem
In display devices, particularly in high-speed operations, the RC load of the clock signal line causes a delay in the gate signal, leading to increased rising and falling times, which degrades the output characteristics.
Innovation Solution
A gate driver is designed with an output clock line and a dummy clock line disposed side by side, where the dummy clock signal is synchronized with the output clock signal to reduce the RC load, thereby minimizing the delay of the output clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the clock signal line is used without dummy lines, then the device complexity is low, but the RC load causes signal delay and degrades output characteristics
Solution Approach 1:
A dummy clock line is introduced as an intermediary element adjacent to the output clock line. This dummy line carries a dummy clock signal that is synchronized with the actual clock signal, creating a coupled system that reduces the effective RC load on the output clock line through electromagnetic coupling and distributed capacitance effects, thereby reducing signal delay without significantly increasing device complexity
Solution Approach 2:
A dummy clock line is created as a copy of the output clock line, positioned adjacent to it. The dummy clock line replicates the electrical characteristics and signal waveform of the original clock line, allowing it to serve as an electromagnetic coupling partner that reduces the RC load effect on the signal transmission through distributed capacitance coupling between the parallel lines
2Productivity
If the frequency is increased for high-speed operation, then the productivity is improved, but the pulse width is reduced and rising/falling times are degraded
Solution Approach 1:
The RC load effect, which normally causes signal delay and degrades rising/falling times, is converted into a beneficial effect by introducing the dummy clock line. The distributed capacitance between the parallel clock lines creates a coupling effect that actually accelerates signal transitions by providing an additional discharge path and reducing the effective time constant, allowing faster operation with maintained pulse width
Data Source
AI summary
A gate driver according to an embodiment and a display device including the same are disclosed. The gate driver according to the embodiment includes an output clock line through which an output clock signal is applied, a dummy clock line disposed side by side with the output clock line and through which a dummy clock signal is applied, a pull-up transistor including a first electrode connected to the output clock line, a gate electrode connected to a first control node, and a second electrode connected to an output node from which a gate signal is output, and a pull-down transistor including a first electrode connected to the output node, a gate electrode connected to a second control node, and a second electrode connected to a power line through which a low-potential power voltage is applied.