Gate Driver Dummy Stages Without a Separate Reset Signal
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Solution Overview
Problem
Existing gate drivers for display devices require a separate reset signal for normal operation, which increases the area of the gate driver and can prevent the size of the display panel from being increased, and also requires precise timing for the reset signal to ensure proper operation.
Innovation Solution
A gate driver is designed with M active stages and K back dummy stages that generate carry and gate signals based on clock signals, allowing the gate driver to operate normally without relying on a separate reset signal. The back dummy stages discharge control nodes based on clock signals, eliminating the need for a separate reset signal line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate reset signal line is added to discharge the control node of the back dummy stage, then the gate driver can operate normally, but the area of the gate driver increases
Solution Approach 1:
The patent merges the reset function with the existing clock signal by using the clock signal to control the discharge of the control node in the back dummy stage. Instead of adding a separate reset signal line, the clock signal is utilized to activate the discharge transistor, thereby eliminating the need for additional signal lines and reducing the gate driver area while maintaining normal operation.
Solution Approach 2:
The clock signal is given multiple functions: it not only drives the normal operation of the shift register stages but also serves as the control signal for discharging the control node in the back dummy stage. This multi-functionality eliminates the need for a dedicated reset signal line, reducing area while ensuring reliable operation.
2Ease of operation
If a separate reset signal is used to discharge the control node, then the operation can be controlled, but the timing must be precise to ensure proper operation
Solution Approach 1:
The clock signal performs dual functions: driving the shift register operation and controlling the discharge of the back dummy stage control node. Since the clock signal timing is already precisely controlled for the main operation, reusing it for the discharge function eliminates the need for additional timing precision requirements for a separate reset signal.
3Ease of manufacture
If the gate driver area is increased to accommodate the reset signal line, then the discharge function can be implemented, but the display panel size cannot be increased
Solution Approach 1:
The discharge function is implemented by merging it with the existing clock signal pathway. The clock signal controls both the normal shift register operation and the discharge of the back dummy stage control node through the discharge transistor, eliminating the need for a separate reset signal line and preventing any increase in display panel size.
Data Source
AI summary
A gate driver includes M active stages configured to generate first through M-th carry signals and first through M-th gate signals based on clock signals, where M is an integer greater than or equal to 4, and K back dummy stages configured to generate (M+1)-th through (M+K)-th carry signals based on the clock signals, where K is an integer greater than or equal to 3. An N-th active stage of the M active stages discharges a control node of the N-th active stage based on an (N+3)-th carry signal, where N is an integer greater than or equal to 1, and is less than or equal to M. At least one back dummy stage of the K back dummy stages discharges a control node of the at least one back dummy stage based on a corresponding clock signal of the clock signals.