Gate Driver Output Protection Using Edge-Delay Fault Detection
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Solution Overview
Problem
Conventional gate driver integrated circuits are susceptible to damage from short circuits and heavy capacitive loads due to slow temperature measurement, making them ineffective in protecting the system from sudden short circuits and high current environments.
Innovation Solution
A method and integrated circuit design that uses a logic circuit to generate an error signal based on the delay between input and output signal edges, allowing for quick detection of short circuits and configuration into a safer operational state, thereby preventing damage from excessive current and heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If temperature sensing is used to detect short circuits, then some protection from damage is provided, but the response is too slow to react to sudden short circuits
Solution Approach 1:
The patent introduces an intermediary mechanism (delay counter) that measures the time delay between input signal edges and output signal edges. This intermediary measurement allows the system to detect short circuits through timing information rather than direct temperature measurement, achieving fast detection without the slow thermal response inherent in temperature sensing.
2Reliability
If current sensing techniques are used, then short circuit detection may be improved, but implementation is difficult in high current environments
Solution Approach 1:
The patent replaces the mechanical/electrical current sensing approach with a timing-based measurement system. Instead of directly measuring high currents (which requires complex current mirrors and precision components), the system measures the temporal delay between input and output signals, substituting a difficult electrical measurement with a simpler timing measurement that can be implemented using standard logic circuits.
3Speed
If delay-based detection is used, then quick detection of short circuits is achieved, but additional circuit complexity is introduced
Solution Approach 1:
The patent implements a self-service mechanism where the gate driver circuit uses its own internal signal timing characteristics to detect faults. The delay counter is integrated within the driver circuit itself, using the natural propagation delay through the output stage as the measurement target. This self-referential approach minimizes external components and keeps the added complexity contained within the existing circuit architecture.
Data Source
AI summary
A method for protecting a system including a driver integrated circuit includes receiving a driver input signal. The method includes driving an output signal externally to the driver integrated circuit. The output signal is driven based on the driver input signal and an indication of a delay between receipt of an edge of the driver input signal and arrival of a corresponding edge of the output signal at an output node coupled to a terminal of the driver integrated circuit.