Gate Driver Circuit for Narrow Bezel Electroluminescent Display
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Solution Overview
Problem
The challenge in electroluminescent displays is to minimize the mounting area of the gate driver while maintaining operation stability, particularly in implementing narrow bezel technology and accommodating freeform display panel shapes without signal distortion.
Innovation Solution
A gate driver is designed with a simplified emission driver configuration, utilizing a plurality of stages with specific transistor configurations and clock signal phases to activate and bootstrap nodes, ensuring efficient signal transmission and stability across varying display panel geometries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the gate driver is directly formed on the lower substrate using GIP manner to reduce mounting area, then the bezel area is reduced, but the operation stability and reliability may be compromised
Solution Approach 1:
The gate driver is divided into two independent drivers: a scan driver and an emission driver. Each driver handles specific gate lines independently, allowing for simplified circuit design and reduced mounting area while maintaining operational reliability through functional separation.
Solution Approach 2:
Different regions of the gate driver are optimized for different functions: the scan driver section handles scanning operations with specific transistor configurations, while the emission driver section handles emission control with bootstrapped nodes. This local optimization allows each section to be minimized for its specific purpose while ensuring overall system stability.
2Area of stationary object
If the emission driver is simplified to reduce mounting area, then the bezel area is reduced, but the signal transmission quality and operation stability may deteriorate
Solution Approach 1:
The bootstrapped nodes (QA, QB) are prepared in advance within each stage of the emission driver. These pre-charged nodes ensure that emission signals are transmitted with proper voltage levels and timing, maintaining signal integrity even with the simplified driver structure and reduced mounting area.
3Productivity
If the transistor configuration is optimized to activate nodes in specific timing, then the emission signal transmission is improved, but the device complexity increases
Solution Approach 1:
The emission driver operates in periodic cycles corresponding to the scanning process. Each stage is activated sequentially by clock signals, with bootstrapped nodes charged and discharged in regular periods. This periodic operation achieves efficient signal transmission through simple repetitive transistor switching patterns rather than complex continuous control.
Solution Approach 2:
The bootstrapped nodes automatically charge and discharge based on the activation of nodes Q and QB in each stage. The circuit uses its own internal nodes and clock signals to control the timing of emission signal transmission without requiring external complex control logic, thereby improving transmission efficiency while maintaining relatively simple device structure.
Data Source
AI summary
A gate driver can include a plurality of stages, each of the plurality of stages including a transistor T1 configured to apply a start signal of a gate-on voltage to a node Q in response to a clock signal and activate the node Q; a transistor T7 configured to supply an emission signal of the gate-on voltage to an output node when a node QA is bootstrapped in synchronization with a timing at which the node Q is activated; a QB controller configured to activate a node QB based on the clock signal, the start signal and a voltage of the node Q; and a transistor T8 configured to supply the emission signal of a gate-off voltage to the output node while the node QB is activated prior to activation of the node Q.