Gate Driver Timing for Display Devices with Extra Outputs

Solution Overview

Problem

Conventional driving methods for liquid crystal display apparatuses face issues with display errors and inability to employ gate drivers with extra outputs due to variations in vertical blank periods, leading to incomplete scans and image deviations.

Innovation Solution

A driving circuit and method that output a gate start pulse signal at the (m−n+k+1)-th line from the beginning of a display period for the previous frame and restart the gate driver clock signal input from the beginning of the next frame, allowing for scanning from a side with extra outputs and managing variations in vertical blank periods.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a gate driver with extra outputs is used to enable opposite direction screen scan, then the adaptability of the display apparatus is improved, but display errors occur when the vertical blank period varies

Engineering Contradiction:

Improvescreen scan direction adaptabilityVSAvoiddisplay accuracy

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The gate start pulse signal is generated in advance during the display period of the previous frame, specifically at the (m−n+k+1)-th line position, rather than during the vertical blank period. This preliminary timing ensures that the gate driver has sufficient time to complete scanning of all outputs including extra ones before the current frame's video signal input begins, preventing display errors even when vertical blank period varies

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The invention dynamically adjusts the gate start pulse signal generation timing based on the relationship between the number of extra outputs (n) and the gate driver clock signal pulses during vertical blank period (k). By calculating the specific line position (m−n+k+1) where to generate the pulse, the system adapts to different gate driver configurations and vertical blank period variations while maintaining reliable display operation

Inventive Principle:

Principle #15Dynamics

2Device complexity

If the gate start pulse signal is generated based on the previous frame, then the timing is simplified, but display errors occur when the vertical blank period varies per frame

Engineering Contradiction:

Improvetiming control complexityVSAvoiddisplay accuracy

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The gate start pulse signal is generated in advance during the display period of the previous frame, specifically at the (m−n+k+1)-th line position, rather than during the vertical blank period. This preliminary timing ensures that the gate driver has sufficient time to complete scanning of all outputs including extra ones before the current frame's video signal input begins, preventing display errors even when vertical blank period varies

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The invention uses feedback from the display data enable signal to detect the end of the vertical blank period and determine the appropriate timing for generating the gate start pulse signal. By monitoring the actual vertical blank period duration and adjusting the pulse generation timing accordingly, the system maintains display accuracy without increasing overall control complexity

Inventive Principle:

Principle #23Feedback

3Duration of action of stationary object

If the gate driver clock signal continues during the vertical blank period, then the scanning is continuous, but the gate start pulse signal timing shifts when the vertical blank period varies

Engineering Contradiction:

Improvegate driver clock signal durationVSAvoidgate start pulse signal positioning

Core Design Contradiction:

Duration of action of stationary objectVSManufacturing precision

Solution Approach 1:

The gate start pulse signal is generated in advance during the display period of the previous frame, specifically at the (m−n+k+1)-th line position, rather than during the vertical blank period. This preliminary timing ensures that the gate driver has sufficient time to complete scanning of all outputs including extra ones before the current frame's video signal input begins, preventing display errors even when vertical blank period varies

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The invention uses periodic gate driver clock signals during the display period to generate the gate start pulse signal at a specific phase (the (m−n+k+1)-th line position). By synchronizing pulse generation with the periodic clock signal rather than relying on continuous operation through the variable vertical blank period, the system maintains precise positioning of the gate start pulse signal

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS8698786B2Driving circuit and driving method for display device

Publication Date: 2014.04.15 NEC LCD TECH CORP

AI summary

A gate start pulse signal for a next frame is output at (m−n+k+1)-th line from a beginning of display period for a previous frame in a case where m denotes the number of the display lines, n denotes the number of extra outputs from the gate driver at a side from which the scan is performed, k denotes a positive integer, and a scan of a gate driver is performed from a side at which there is an extra output from the gate driver; k pulses of gate driver clock signals are output during a vertical blank period; and input of a gate driver clock signal is restarted from a beginning of a display period for the next frame.