Gate Driver Shift Register Layout for Fast Scanning Signal Fall
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Solution Overview
Problem
In large-sized and high-definition liquid crystal display devices with monolithic gate drivers, the increased load capacitance of gate bus lines leads to a prolonged time for scanning signals to fall, causing display failures due to color mixture between rows, as the charge time per line becomes shorter.
Innovation Solution
A scanning signal line drive circuit with multiple shift registers, where each shift register operates based on cyclically repeating clock signals with different level change timings, includes bistable circuits with output control switching elements and node turn-on/off units to ensure quick fall of scanning signals after charge periods, using thin-film transistors that can maintain nodes in an on state during phase differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the panel size is increased, then the display area is enlarged, but the load capacitance of gate bus lines increases causing scanning signal fall time to prolong
Solution Approach 1:
The gate driver is divided into multiple shift registers (first shift register and second shift register) that operate alternately. Each shift register drives a subset of gate bus lines, allowing the scanning signal to be reset more quickly by switching between registers. This segmentation resolves the contradiction by maintaining large display area while reducing individual signal line load and fall time.
Solution Approach 2:
The gate driver uses periodic alternation between two shift registers to drive different sets of gate bus lines in different time periods. During one period, the first shift register drives odd-numbered lines while the second shift register drives even-numbered lines, and they switch roles in the next period. This periodic action allows each register to reset its output quickly during its non-active period, solving the fall time issue while maintaining large panel support.
2Productivity
If the charge time per line is reduced for high-definition display, then the scanning speed is improved, but the scanning signal may not fall to low level in time causing color mixture
Solution Approach 1:
The output control switching element is configured to reset the scanning signal to low level in advance during the period when the next row is being charged. While one shift register is actively charging a row, the other shift register prepares by resetting its output signal. This preliminary action ensures that when the active register finishes charging, its signal has already fallen to low level, preventing color mixture and maintaining display accuracy during high-speed operation.
Solution Approach 2:
The output control switching element acts as an intermediary between the shift register and the gate bus line. It controls the timing of the scanning signal by enabling the shift register output during the charge period and disabling it (resetting to low level) during the next row's charge period. This intermediary function allows fast charging while ensuring proper signal fall timing, resolving the contradiction between charge speed and display accuracy.
3Ease of manufacture
If a monolithic gate driver is used, then the packaging yield is improved and cost is reduced, but the circuit complexity increases making it difficult to ensure quick signal fall
Solution Approach 1:
The monolithic gate driver is segmented into multiple independent shift register units (first and second shift registers) with distinct functional blocks. Each shift register contains its own bistable circuits, output control switching elements, and timing control mechanisms. This segmentation reduces the complexity of controlling the entire driver by allowing independent design and optimization of each unit, while still achieving the monolithic integration benefits for packaging yield and cost reduction.
Data Source
AI summary
It is an object to realize a gate driver that can cause a scanning signal to quickly fall after a charge period in each row ends.A gate driver is configured by two shift registers. In an n-th stage bistable circuit (SR(n)) in an entire shift register (410), a region netA connected to a gate terminal of a thin-film transistor that increases a potential of an output node for outputting a state signal (Q) based on a first clock (CKA) is set to an on level based on the state signal (Q) outputted from an (n−2)-th stage bistable circuit (SR(n−2), the region netA is set to an off level based on the state signal (Q) outputted from an (n+2)-th stage bistable circuit (SR(n+2)), and the output node is set to an off level based on the state signal (Q) outputted from an (n+3)-th stage bistable circuit (SR(n+3)).