Gate Driver Circuit Dynamic Shift Register Fault Handling
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Solution Overview
Problem
Current gate driver architectures for narrow-border displays are limited by the size of the gate IC, leading to increased costs and labor due to the need for multiple driver boards to accommodate potential shift register damage during manufacturing, which can result in abnormal display issues.
Innovation Solution
A gate driver circuit with a potential enhancing unit, switch unit, current detecting unit, and control unit that divides clock signals into two groups, detects current output, and dynamically switches off damaged shift registers, allowing for unilateral driving and improving compatibility and reducing design costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple driver boards are developed to accommodate potential shift register damage, then reliability is improved, but device complexity and design costs increase
Solution Approach 1:
The driver board is designed with a switch unit that can dynamically configure the clock signal distribution topology, enabling the same hardware to function in multiple modes (unilateral left, unilateral right, or bilateral driving) based on actual shift register status, thereby eliminating the need for multiple specialized driver board versions
Solution Approach 2:
The driver board incorporates a switch unit controlled by a control unit that can dynamically adjust the clock signal distribution configuration in real-time based on feedback from current detecting units, allowing the system to adapt to shift register damage conditions without requiring physical hardware changes or multiple pre-configured board versions
2Adaptability or versatility
If three different driver boards are developed for different driving modes, then adaptability to damage states is improved, but manufacturing cost and labor increase
Solution Approach 1:
A single driver board design incorporates a reconfigurable clock signal distribution mechanism with switch units that can be programmed to operate in different driving modes (unilateral left, unilateral right, or bilateral), allowing one universal board design to replace three specialized board designs and simplify the manufacturing supply chain
Solution Approach 2:
The driver board uses controllable switch units whose on/off states can be dynamically adjusted to change the signal distribution parameters, enabling the same physical hardware to adapt to different damage scenarios through parameter reconfiguration rather than requiring different hardware designs
3Reliability
If passive determination of working driver board is used based on actual damage status, then reliability is maintained, but time consumption and labor cost increase
Solution Approach 1:
The driver board incorporates current detecting units that continuously monitor the operational status of shift registers and provide real-time feedback to the control unit, enabling automatic detection of damage conditions and dynamic reconfiguration of the driving mode without requiring manual inspection or passive determination
Solution Approach 2:
The driver board system performs self-diagnosis through current detection and automatically reconfigures its operating mode through the control unit and switch units when damage is detected, eliminating the need for external intervention or manual determination of the working configuration
Data Source
AI summary
Disclosed are a gate driver circuit, a level shifter and a display apparatus. The gate driver circuit includes a potential enhancing unit, a switch unit, a current detecting unit, and a control unit. The potential enhancing unit is configured to divide a clock signal output by a timing sequence controller into two clock signal groups after the clock signal being potential enhanced, and correspondingly output the two clock signal groups to two shift register groups; the switch unit is configured to control to output or stop outputting the clock signal groups; the current detecting unit is configured to respectively detect output current of each sub-clock signal; the control unit is configured to compare current values corresponding to the plurality of current signals with a preset current threshold respectively, output a control signal to the switch unit.