Gate Driver Multifunction Pin for Fault Reset and Test Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current gate drivers for high-power switching systems are complex and costly due to the need for multiple pins to communicate auxiliary functions such as fault detection, reset, and testing, which increases size and complexity.
Innovation Solution
A multifunction signal pin is used to combine enable, reset, and fault check signals, allowing the gate driver to perform switching, fault sensing, and testing functions, reducing the number of pins required and simplifying communication with a microcontroller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple pins are used for enable, reset, and fault check signals, then communication functionality is complete, but device complexity and size increase
Solution Approach 1:
The patent applies multi-functionality by enabling a single pin to perform multiple roles: normal operation signal input, fault detection trigger, and test mode activation. The pin accepts different signal patterns (continuous levels vs. transient pulses) to distinguish between normal control signals and test/fault signals, eliminating the need for separate dedicated pins for each function while maintaining complete communication capability
Solution Approach 2:
The patent merges previously separate functions (enable, reset, fault check) into a single pin interface. By combining these functions and using signal pattern recognition to differentiate between them, the design reduces the pin count while preserving all necessary communication functionalities between the gate driver and microcontroller
2Reliability
If multiple pins are used for auxiliary functions, then fault detection capability is complete, but manufacturing cost increases
Solution Approach 1:
The same multi-functionality principle reduces manufacturing cost by minimizing the pin count. Fewer pins mean simpler packaging, reduced PCB real estate requirements, and lower overall system cost while the fault detection capability remains intact through the integrated signal handling approach
Solution Approach 2:
By merging fault detection functionality into the existing multifunction pin rather than requiring a separate dedicated fault pin, the design reduces component count and assembly complexity, directly impacting manufacturing cost reduction while maintaining complete fault detection capability
3Reliability
If multiple pins are used for communication, then testing capability is complete, but device size increases
Solution Approach 1:
The test mode activation through the multifunction pin demonstrates universality, where the same pin interface handles normal operation, fault detection, and comprehensive testing functions. The gate driver automatically enters test mode when detecting specific pulse patterns, enabling complete testing capability without requiring additional test-specific pins or increasing device footprint
Solution Approach 2:
By combining testing functionality with the existing multifunction pin rather than adding separate test pins, the design maintains complete testing capability while minimizing device size. The integration of test functions into the primary communication interface eliminates the need for additional physical space that separate test pins would require
Data Source
Figure 1A
Figure 1B
Figure 2A
AI summary
A gate driver to control a high-power switching device is disclosed. The gate driver includes a multifunction pin that allows the gate driver to be controlled by a multifunction signal to perform a number of different functions. For example, a level of the multifunction signal at the multifunction pin can enable/disable the output of the gate driver. In another example, a level of the multifunction signal that is held for a period while the gate driver is in a fault state can reset the state of the gate driver. In another example, pulsing the multifunction signal a number of times can activate a test of the fault detection capabilities of the gate driver. Utilizing one pin for this control, simplifies circuit complexity for communication between a controller and the gate driver, thereby reducing cost and increasing reliability.