Gate Driver Fault Identification Through Timed Shared Output
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Solution Overview
Problem
Existing gate driver systems lack the ability to identify which of multiple gate drivers has reported a fault without increasing the number of I/O pins, as all fault output nodes are typically connected to a single I/O pin, making it difficult to determine the specific driver causing the fault.
Innovation Solution
Implementing a timing arrangement for each gate driver that sets a common node to a fault state and releases it after a predetermined time period unique to each driver, allowing identification by measuring the time between the trigger event and the common node's release from the fault state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If all fault output nodes are connected to a single I/O pin, then the number of I/O pins is reduced, but the ability to identify which gate driver reported the fault is lost
Solution Approach 1:
Each gate driver is pre-configured with a unique time delay value stored in its timing arrangement. When a fault occurs, the gate driver automatically activates its timing arrangement, which delays the assertion of the common fault signal by its unique time period. This preliminary setup of distinct time characteristics allows the controller to identify the fault source by measuring the delay, resolving the contradiction between using fewer pins and maintaining fault identification capability.
2Measurement precision
If each gate driver uses a unique time delay, then fault identification is enabled, but the device complexity increases
Solution Approach 1:
Instead of adding complex hardware differentiation, the invention changes the temporal parameter of the fault signal by assigning unique time delays to each gate driver. This parameter-based differentiation allows precise fault identification while maintaining relatively simple timing arrangement circuitry, thus achieving high measurement precision without excessive device complexity.
Solution Approach 2:
The invention replaces potential complex hardware identification mechanisms (such as separate pins or switches) with a temporal encoding scheme implemented through timing arrangements. This substitution uses time-based signaling instead of spatial or mechanical differentiation, simplifying the overall system architecture while maintaining precise fault identification capability.
Data Source
AI summary
A gate driver system includes a plurality of gate drivers, each gate driver having a fault output node switchable between a fault state indicating a detected fault by the respective gate driver and an operating state. Timing arrangements are provided for each of the gate drivers, with each timing arrangement configured to switch a common node to a first state, responsive to the fault output node of the respective gate driver being set to the fault state (e.g., responsive to a trigger event). Then, after a predetermined time period having elapsed from a trigger event, the common node is released from the first state. As the predetermined time period for each of the timing arrangements is different, the amount of time between the trigger event and the common node being released from the first state may be measured to identify which gate driver among gate drivers that reported a fault.