Gate Driver Frequency Segmentation for Partial-Panel Power Reduction

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Solution Overview

Problem

Conventional display devices with low-frequency driving technology do not effectively reduce power consumption when still images are displayed in partial areas, as the entire panel is driven at a general frequency, leading to unnecessary power usage.

Innovation Solution

A gate driver with a control circuit and gate output circuit that includes a first control switching element to selectively connect nodes in response to an enable signal, allowing for driving frequency multi-division, thereby reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the entire display panel is driven at a general driving frequency, then the display performance is maintained, but the power consumption increases unnecessarily when only partial areas display still images

Engineering Contradiction:
Improvepower consumptionVSAvoiddriving frequency adjustment capability
Core Design Contradiction:
Use of energy by moving objectVSAdaptability or versatility

Solution Approach 1:

The gate driver is divided into multiple independent stages, each capable of operating at different frequencies. The control circuit selectively activates specific stages based on the display content distribution, allowing partial area low-frequency driving while maintaining general driving frequency in other regions, thus reducing overall power consumption without sacrificing display performance

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The gate driver implements dynamic frequency adjustment capability where the driving frequency can be changed based on real-time display content analysis. When still images are detected in specific regions, those regions are switched to low-frequency mode, while other regions continue operating at general frequency, achieving adaptive power management

Inventive Principle:
Principle #15Dynamics

2Use of energy by moving object

If low-frequency driving is implemented, then power consumption is reduced, but the gate driver requires additional control mechanisms to manage different frequency modes

Engineering Contradiction:
Improvepower consumptionVSAvoidcontrol circuit complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The control circuit integrates multiple functions including frequency selection, stage activation control, and display content analysis into a unified control mechanism. This merged approach manages different frequency modes through a single coordinated system rather than separate independent controls, reducing overall control complexity while enabling low-frequency driving capability

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The control circuit is designed with multi-functionality to handle both general frequency driving and low-frequency driving modes, as well as to manage multiple stages simultaneously. This universal control mechanism reduces the need for separate dedicated control circuits for each function, thereby limiting the increase in device complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentEP4593002A1Gate driver, display device including the gate driver, and electronic device including the display device
Publication Date: 2025.07.30 SAMSUNG DISPLAY CO LTD
  • EP4593002A1 patent drawingFigure 1
  • EP4593002A1 patent drawingFigure 2
  • EP4593002A1 patent drawingFigure 3

AI summary

A gate driver includes: a plurality of stages. Each of the stages includes: a control circuit configured to control a voltage of a first node and a voltage of a second node in response to an input signal, a first clock signal, and a second clock signal; and a gate output circuit configured to output a gate signal in response to the voltage of the first node and the voltage of the second node. The control circuit includes a first control switching element configured to selectively connect the first node and the gate output circuit in response to an enable signal.