Gate Driver Shift Register Layout for Half-Period Signal Alignment
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Solution Overview
Problem
The existing gate driving circuits for display panels require duplicating components and increasing layout area to achieve the necessary timing alignment of gate signals, leading to larger display panel sizes due to the need for alternating arrangements of shift registers and duplicated wiring.
Innovation Solution
The proposed gate driving circuit design includes Nth and (N+1)th shift registers with specific pull-up and pull-down units, utilizing clock signals and capacitive coupling to achieve the required timing alignment without duplicating shift register stages, thereby reducing component count and layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If components and wires of the Nth shift register are duplicated in layout to achieve timing separation, then gate signal timing alignment is improved, but layout area and component number increase
Solution Approach 1:
The patent merges the functionality of duplicated shift register stages into a single integrated circuit structure. The Nth and (N+1)th shift registers share common clock signal routing and are implemented in a compact arrangement, eliminating the need for separate duplicated layouts while maintaining the required timing separation between gate signals.
Solution Approach 2:
The patent transitions from a one-dimensional sequential layout approach to a two-dimensional integrated arrangement. By organizing the shift register stages in a planar configuration with shared resources and optimized signal routing, the design achieves timing separation without proportionally increasing layout area.
2Manufacturing precision
If each stage of shift register is laid out twice to separate gate signals by half period, then timing separation is improved, but device complexity increases
Solution Approach 1:
The patent implements multi-functionality within the shift register stages, where common components serve multiple purposes. The clock signal distribution network and control logic are designed to handle timing separation for multiple stages simultaneously, reducing the total component count while achieving the required half-period timing separation between adjacent gate signals.
3Manufacturing precision
If shift register stages are arranged in alternating order for clock signal reception, then timing alignment is improved, but routing complexity increases
Solution Approach 1:
The patent segments the clock signal distribution into dedicated phases, with even-numbered stages receiving one clock phase and odd-numbered stages receiving another. This segmentation allows systematic routing patterns that reduce complexity compared to alternating arrangements, while maintaining precise timing alignment through phase-separated clock distribution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design allows for efficient timing alignment of gate signals, reducing the need for duplicate shift register layouts and simplifying the routing of clock signals, thus minimizing the overall size and complexity of the gate driving circuit.
Implementation Method 1
utilizing clock signals and capacitive coupling to achieve the required timing alignment
Implementation Method 2
The first pull down unit is used for pulling down the first pull up signal according to the first clock signal
Data Source
AI summary
An Nth shift register includes a pull up unit, a driving unit, a first pull down unit, a second pull down unit, and a third pull down unit. The pull up unit is used for providing a first pull up signal according to a first clock signal, a second clock signal, and a starting pulse. The driving unit is used for providing a driving signal according to the first pull up signal and providing a gate signal according to the first clock signal and the driving signal. The first pull down unit is used for pulling down the first pull up signal according to the first clock signal. The second pull down unit is used for pulling down the driving signal according to a second pull up signal. The third pull down unit is used for pulling down the gate signal according to the second clock signal.