Gate Driver Hold-Capacitor Circuit for Stable Gate Signals
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Solution Overview
Problem
The reliability of gate drivers in display devices is compromised when transistors within the stages are damaged, leading to the inability to generate normal gate signals.
Innovation Solution
The gate driver design includes a first pull-up control circuit, a buffer circuit, and a pull-down circuit, with a hold capacitor connected between the second control node and a constant voltage line, ensuring the second control node maintains a high gate voltage even when the previous carry signal transitions to low, thereby preventing a decrease in on-current and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the previous carry signal transitions to low voltage, then the gate driver can reset the control node, but the on-current of the transistor decreases leading to reduced reliability
Solution Approach 1:
The hold capacitor is charged to a constant voltage level in advance during the previous cycle. When the carry signal transitions to low, this pre-charged capacitor immediately maintains the control node at the high voltage level, preventing the transient voltage drop that would otherwise reduce transistor on-current. This preliminary charging action ensures continuous reliable operation without current depletion.
2Reliability
If the control node voltage drops when carry signal transitions to low, then the transistor can be properly reset, but the gate signal generation becomes unstable
Solution Approach 1:
The hold capacitor acts as an intermediary energy storage element between the carry signal and the control node. Instead of allowing the control node voltage to freely follow the carry signal transitions, the capacitor mediates this relationship by maintaining a constant voltage level during transitions, thereby stabilizing the control node voltage and ensuring stable gate signal generation while still allowing proper reset functionality.
Data Source
AI summary
A gate driver includes stages, each including a first pull-up control circuit configured to apply a previous carry signal to a first control node, a buffer circuit configured to output a gate clock signal as a gate output signal, and a pull-down circuit configured to output a second low voltage as the gate output signal. The first pull-up control circuit includes a 4-1st transistor including a control electrode, a first electrode, and a second electrode connected to a second control node. The first pull-up control circuit includes a 4-2nd transistor including a control electrode, a first electrode connected to the second control node, and a second electrode connected to a first control node. The first pull-up control circuit includes a hold capacitor including a first electrode connected to the second control node and a second electrode configured to receive a constant voltage.