Gate Driver Stage Circuit With Inter-Node Capacitors for Signal Reliability
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Solution Overview
Problem
The reliability of gate drivers in display devices is compromised when transistors within the stages are damaged, leading to the inability to generate normal gate signals.
Innovation Solution
A gate driver design incorporating a first pull-up control circuit, buffer circuit, and pull-down circuit with inter-node capacitors to stabilize voltage levels and prevent on-current decrease in transistors, ensuring reliable gate signal generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a transistor in each stage is damaged, then the stage cannot generate normal gate signals, but adding protection circuits increases device complexity
Solution Approach 1:
The patent applies beforehand cushioning by introducing a first pull-up control circuit that proactively maintains the first control node at a first high voltage level before damage occurs. This control circuit includes a first pull-up transistor and a first capacitor that stores charge to ensure the control node remains at the required voltage level even if subsequent transistors fail, thereby preventing damage propagation and maintaining gate signal generation capability.
Solution Approach 2:
The patent uses an intermediary approach by introducing a first control node as an intermediate element between the carry signal input and the gate output. This control node is regulated by the first pull-up control circuit to maintain stable voltage levels, acting as a buffer that isolates the rest of the circuit from potential damage while ensuring proper gate signal generation.
2Reliability
If inter-node capacitors are added to maintain stable transistor operation, then reliability improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies parameter changes by carefully selecting and optimizing the capacitance values of the first and second capacitors. The first capacitor is configured to maintain the first control node at a first high voltage level, while the second capacitor maintains the second control node at a second high voltage level. By optimizing these parameter values, the circuit achieves stable transistor operation without requiring excessive manufacturing precision, as the capacitor values can be standard components within acceptable tolerance ranges.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances the reliability of gate drivers by maintaining stable transistor performance, preventing voltage fluctuations, and ensuring consistent gate signal output.
Implementation Method 1
a first inter-node capacitor including a first electrode connected to the previous carry input node and a second electrode connected to the second control node, and a second inter-node capacitor including a first electrode connected to the second control node and a second electrode connected to the first control node
Data Source
AI summary
Each of stages of a gate driver includes a first pull-up control circuit applying a previous carry signal to a first control node, a buffer circuit outputting a gate clock signal, and a pull-down circuit outputting a second low voltage. The first pull-up control circuit includes a fourth-first transistor including a control electrode connected to a previous carry input node, a first electrode connected to the previous carry input node, and a second electrode connected to a second control node, a fourth-second transistor including a control electrode connected to the previous carry input node, a first electrode connected to the second control node, and a second electrode connected to the first control node, a first inter-node capacitor connected between the previous carry input node and the second control node, and a second inter-node capacitor connected between the second control node and the first control node.