Gate Driver Circuit for PMOS/NMOS Inverted Signal Output
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Solution Overview
Problem
The increasing complexity of flat panel display devices due to the inclusion of both PMOS and NMOS transistors leads to higher power consumption and increased dead space, necessitating a more efficient gate driver solution.
Innovation Solution
A gate driver is designed with a signal generator and an inverted signal generator, utilizing PMOS and NMOS transistors in series, to generate and output gate signals and inverted gate signals with the same voltage level, reducing the need for multiple gate drivers and minimizing dead space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If both PMOS and NMOS transistors are included in the pixel, then the display device can drive both types of transistors, but power consumption and dead space increase due to the need for an additional gate driver
Solution Approach 1:
The patent combines the functions of driving both PMOS and NMOS transistors into a single gate driver unit. The gate driver includes a first transistor (PMOS) and a second transistor (NMOS) that work together to generate both normal gate signals and inverted gate signals, eliminating the need for separate gate drivers for each transistor type and thereby reducing power consumption.
Solution Approach 2:
The gate driver is designed with multi-functionality to drive both PMOS and NMOS transistors using a single unit. By incorporating both PMOS and NMOS transistors within the gate driver itself, the system can generate multiple types of gate signals (normal and inverted) from one device, making the gate driver universal for driving different transistor types in the pixel.
2Adaptability or versatility
If both PMOS and NMOS transistors are included in the pixel, then the display device can drive both types of transistors, but dead space increases due to the need for an additional gate driver
Solution Approach 1:
The patent combines the functions of driving both PMOS and NMOS transistors into a single gate driver unit. The gate driver includes a first transistor (PMOS) and a second transistor (NMOS) that work together to generate both normal gate signals and inverted gate signals, eliminating the need for separate gate drivers for each transistor type and thereby reducing dead space.
Solution Approach 2:
The gate driver is designed with multi-functionality to drive both PMOS and NMOS transistors using a single unit. By incorporating both PMOS and NMOS transistors within the gate driver itself, the system can generate multiple types of gate signals (normal and inverted) from one device, making the gate driver universal for driving different transistor types in the pixel and reducing the area required.
3Use of energy by stationary object
If a single gate driver is used to generate both gate signals and inverted gate signals, then power consumption and dead space are reduced, but the circuit complexity increases
Solution Approach 1:
The gate driver is segmented into distinct functional components: a signal generator for generating gate signals and an inverted signal generator for generating inverted gate signals. Each generator uses a specific transistor type (PMOS for normal signals, NMOS for inverted signals), allowing the complex function to be divided into manageable segments that can be independently controlled and optimized.
Solution Approach 2:
The inverted signal generator uses an NMOS transistor to generate inverted gate signals, while the normal signal generator uses a PMOS transistor. This inversion approach allows the circuit to generate both normal and inverted signals efficiently within a single gate driver, managing complexity through complementary transistor operations.
Data Source
AI summary
A gate driver includes: a signal generator configured to generate a gate signal, and output the gate signal to a first output terminal; and an inverted signal generator configured to generate an inverted gate signal based on the gate signal, and output the inverted gate signal to a second output terminal, wherein the inverted signal generator includes: a first transistor connected between a first node connected to the second output terminal and a first driving power supply terminal, and including a PMOS transistor; and a second transistor connected between the first node and a second driving power supply terminal, and including an NMOS transistor, and wherein a second node connected to the first output terminal is connected to a gate electrode of each of the first and second transistors.