Gate Driver Kickback Compensation for RC Delay in Display Panels
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Solution Overview
Problem
In display apparatuses with gate and data drivers disposed adjacent to one side of the panel, resistance-capacitance (RC) delay variations lead to inconsistent charging rates, luminance, afterimage, and flicker across the display panel, degrading display quality.
Innovation Solution
The display apparatus includes a gate driver and data driver positioned adjacent to one side, with gate lines and data lines configured to adjust kickback slices and source shifts based on position, using a timing controller and power voltage generator to generate compensated gate signals and voltages, ensuring uniformity in charging rates and luminance across the panel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If gate and data drivers are disposed adjacent to only one side of the display panel, then the bezel width is reduced, but RC delay variations cause inconsistent charging rates and luminance across the panel
Solution Approach 1:
The patent applies local quality by adjusting the kickback slice duration of gate signals based on the positional RC delay characteristics of different regions of the display panel. Specifically, gate signals applied to positions with low RC delay have a longer kickback slice duration, while gate signals applied to positions with high RC delay have a shorter kickback slice duration. This localized adjustment compensates for the non-uniform RC delay effects across the panel, maintaining consistent charging rates and luminance despite the drivers being positioned at only one side.
2Manufacturing precision
If gate signal kickback slice is increased to compensate for RC delay, then charging rate uniformity is improved, but the gate signal complexity increases
Solution Approach 1:
The patent employs parameter changes by dynamically adjusting the kickback slice duration parameter of gate signals based on the RC delay characteristics of different positional groups. The timing controller divides the display panel into multiple positional groups and assigns different kickback slice durations to each group, thereby compensating for RC delay variations without requiring complex additional hardware circuits.
Data Source
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AI summary
A display apparatus includes a display panel, a gate driver and a data driver. The display panel includes gate lines, data lines and pixels electrically connected to the gate lines and the data lines. The gate driver is disposed adjacent to a first side of the display panel, and outputs a gate signal to the gate line. The data driver is disposed adjacent to the first side of the display panel, and outputs a data voltage to the data line. A gate signal applied to a position having a low resistance-capacitance ("RC") delay of the gate line has a kickback slice greater than a kickback slice of a gate signal applied to a position having a high RC delay of the gate line. The kickback slice is defined as a portion having a level lower than a gate-on voltage level in a gate pulse of the gate signal.