Gate Driver Layout Optimization for Free-Form Display Non-Display Area Reduction
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Solution Overview
Problem
In display apparatuses with embedded gate drivers, the non-display area is increased due to the need for additional gate stages and wiring, especially in free-form panels with hetero-transistors, which complicates the layout and increases the bezel ratio, making it difficult to minimize the size of the non-display area.
Innovation Solution
The gate driver is optimized by configuring gate blocks with multiple stages, including a first scan driving circuit, a second scan driving circuit, an emission driving circuit, a switching driving circuit, and a reset driving circuit, and disposing them in a non-standard, atypical arrangement within the non-display area to minimize space, with a low potential power line placed between the gate driver and the outer periphery to reduce interference and optimize space usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate driver is embedded in the display panel with hetero-transistors, then the display performance is improved, but the non-display area is increased
Solution Approach 1:
The gate driver is divided into multiple gate stages (first gate stage, second gate stage, third gate stage) that are distributed and connected through link lines. This segmentation allows the gate driver to be distributed across the display panel rather than concentrated in one location, reducing the local non-display area while maintaining the functionality required for hetero-transistor operation.
Solution Approach 2:
The gate driver utilizes vertical stacking of transistor layers (first through fifth transistor layers) to accommodate multiple gate stages within the same planar footprint. By utilizing the vertical dimension through layered structures, the patent reduces the horizontal space required for the gate driver, thereby minimizing the non-display area while supporting hetero-transistor functionality.
2Adaptability or versatility
If the number of gate stages is increased to support hetero-transistors, then the driving capability is improved, but the layout complexity is increased
Solution Approach 1:
Multiple gate stages are integrated into a unified gate driver structure that shares common components such as the fifth transistor layer and link line routing patterns. The first, second, and third gate stages utilize overlapping transistor layers and standardized connection patterns, which reduces layout complexity while maintaining the enhanced driving capability required for hetero-transistor operation.
Solution Approach 2:
The gate driver design incorporates universal transistor layers (particularly the fifth transistor layer) that serve multiple gate stages simultaneously. This multi-functional approach allows a single layer structure to support multiple gate functions, reducing the overall layout complexity while providing the versatile driving capability needed for both LTPS and oxide semiconductor transistors.
3Ease of operation
If the gate driver extends in the horizontal direction to ensure space for wiring lines, then the connectivity is improved, but the non-display area is increased
Solution Approach 1:
The patent transitions from horizontal extension to vertical stacking by utilizing multiple transistor layers (first through fifth layers) to route wiring lines and connect gate stages. This vertical dimensionality change allows adequate spacing for wiring lines while minimizing the horizontal footprint of the gate driver, thereby reducing the non-display area while maintaining connectivity.
Solution Approach 2:
The gate driver employs a nested structure where link lines are routed through and between transistor layers, with wiring lines nested within the layered architecture. This nesting approach allows multiple wiring paths to coexist within the same planar area without requiring additional horizontal space, thus maintaining connectivity while minimizing the non-display area.
Data Source
AI summary
A display apparatus can include a display area including pixel rows, the display area having an outer periphery including a curved section and a straight section; a non-display area surrounding the display area, the non-display area having an outer periphery including a curved section and a straight section; a gate driver disposed in the non-display area, the gate driver including gate blocks corresponding to the pixel rows; and a low potential power line disposed between the gate driver and the outer periphery of the non-display area, in which each of the gate blocks includes a plurality of stages.