Gate Driver IC Layout for Negative Voltage Surge Mitigation
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Solution Overview
Problem
Existing three-phase one-chip gate driver ICs are prone to malfunction due to negative voltage surges, as electrons flow into high side driver circuits of adjacent phases, leading to increased chip size and ineffective malfunction prevention methods for three-phase systems.
Innovation Solution
The semiconductor device incorporates two set and reset level shift circuits with level shift elements disposed on non-opposed surfaces, ensuring equal or greater than 150 μm distance from pn junction surfaces to high potential regions, reducing electron flow and preventing high side driver circuit malfunctions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If level shift elements are disposed on opposed surfaces to reduce chip area, then area is reduced, but negative voltage surge causes electrons to flow into adjacent phases causing malfunction
Solution Approach 1:
The patent transitions from a two-dimensional planar layout to a three-dimensional vertical structure by forming n-well regions at different depths within the semiconductor substrate. The first n-well region for the first phase is formed at a first depth, while the second n-well region for the adjacent phase is formed at a second depth greater than the first depth. This vertical separation in the depth dimension effectively isolates the phases from each other, preventing electron flow during negative voltage surges while maintaining compact chip area.
Solution Approach 2:
The patent segments the semiconductor substrate into multiple isolated n-well regions at different depths, each containing a separate high side driver circuit for a different phase. The first n-well region and second n-well region are spatially separated both horizontally and vertically, creating electrically isolated compartments that prevent cross-phase interference while maintaining integration on a single chip.
2Reliability
If distance between phases is increased to prevent electron flow, then reliability is improved, but chip area increases
Solution Approach 1:
Instead of increasing horizontal distance between phases which would expand chip area, the patent utilizes the vertical depth dimension to create separation. By forming n-well regions at different depths (first depth vs. second depth), the patent achieves effective isolation against electron flow during negative voltage surges without requiring additional horizontal space, thus maintaining compact chip area while improving reliability.
Data Source
AI summary
In a semiconductor device such as a three-phase one-chip gate driver IC, HVNMOSs configuring two set and reset level shift circuits are disposed on non-opposed surfaces, and it is thereby possible to reduce the amount of electrons flowing into drains of HVNMOSs of another phase due to a negative voltage surge. Also, distances from an opposed surface on the opposite side to the respective drains of the HVNMOSs configuring the two set and reset level shift circuits are made equal to or more than 150 μm, and it is thereby possible to prevent a malfunction of a high side driver circuit of another phase to which no negative surge is applied.