Gate Driver Leakage Current Reduction via Segmented Shift Registers
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Solution Overview
Problem
Conventional gate driver circuits in LCDs using amorphous silicon or Indium-Gallium-Zinc Oxide materials suffer from significant leakage currents, leading to output signal ripples and increased power consumption, which necessitate additional voltage stabilization circuits, thereby increasing power consumption and circuit layout area.
Innovation Solution
A gate driver comprising cascade-connected driving stages with shift register circuits and switches that output multiple gate signals sequentially, utilizing pull-down units to stabilize voltages and reduce leakage currents, allowing for efficient operation with fewer stages and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional gate driver circuits use amorphous silicon or Indium-Gallium-Zinc Oxide materials for transistor switches, then the circuit can be implemented on glass substrate, but significant leakage currents occur leading to output signal ripples and increased power consumption
Solution Approach 1:
The gate driver circuit is divided into multiple independent driving stages, where each stage processes and stabilizes signals separately before output. This segmentation allows leakage currents in individual stages to be controlled and isolated, preventing cumulative ripple effects while maintaining overall circuit functionality on glass substrate
Solution Approach 2:
Voltage stabilization is performed in advance within each driving stage before signals are output to gate lines. The stabilization circuit proactively compensates for leakage currents and prevents ripple formation, rather than attempting to correct issues after they occur, thereby reducing power consumption while ensuring signal quality
2Stability of the object's composition
If additional voltage stabilizing circuits are added to reduce output signal ripples, then signal stability improves, but power consumption and circuit layout area increase
Solution Approach 1:
The voltage stabilization function is merged into each driving stage itself rather than being implemented as separate additional circuits. By integrating the stabilization capability within the existing stage structure, the circuit achieves signal stability without proportionally increasing layout area, as the stabilization components share space with the driving elements
Solution Approach 2:
Each driving stage is designed to perform multiple functions: signal amplification, voltage stabilization, and ripple suppression. This multi-functionality eliminates the need for dedicated separate stabilization circuits, reducing overall circuit complexity and layout area while maintaining output signal stability
3Loss of energy
If multiple gate signals are outputted by a single driving stage, then the number of stages is reduced and power consumption decreases, but the circuit design complexity increases
Solution Approach 1:
Each driving stage is designed as a universal module capable of outputting multiple gate signals simultaneously to different gate lines. This multi-functional design allows a reduced number of stages to drive the entire display panel, decreasing total power consumption while the modular universal design actually simplifies rather than complicates the overall circuit architecture
Solution Approach 2:
The circuit utilizes different clock signal phases and timing parameters to enable a single stage to generate multiple distinct gate signals. By manipulating temporal parameters rather than adding spatial complexity, the circuit achieves reduced stage count and power consumption without proportionally increasing design complexity
Data Source
AI summary
A gate driver includes cascade-connected driving stages. Each of the driving stages includes a first shift register circuit and a second shift register circuit. The first shift register circuit is configured for outputting a present stage driving signal and a next stage driving signal. The second shift register circuit is electrically coupled to the first shift register circuit and configured for outputting a present stage gate signal, a first next stage gate signal, and a second next stage gate signal. Furthermore, a display panel is also provided herein.