Gate Driver Level Shifting for Faster Signal Transitions
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Solution Overview
Problem
The reliability of gate drivers in display devices is compromised due to slow rising and falling transitions of control node signals, leading to deteriorated performance.
Innovation Solution
A gate driver design incorporating transistors and capacitors that enhance signal transitions by utilizing a level shifter and transistors configured to respond to control node signals, reducing signal amplitudes and incorporating a previous carry signal to improve transition times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate driver design is used, then the structure is simple, but the rising and falling transitions of control node signals are too slow, deteriorating reliability
Solution Approach 1:
The gate driver is divided into multiple stages (first stage, second stage, third stage) with each stage handling specific transition tasks. The first stage handles initial charging, the second stage handles main charging, and the third stage handles final charging, allowing each stage to be optimized independently for speed while managing overall complexity.
Solution Approach 2:
The level shifter pre-charges the control node signal before it reaches the gate driver stages. By preparing the signal in advance with appropriate voltage levels, the subsequent charging stages can operate more efficiently and achieve faster transitions without requiring excessive complexity in each individual stage.
2Speed
If the gate driver uses higher voltage swings to speed up transitions, then transition speed improves, but power consumption increases
Solution Approach 1:
The level shifter dynamically adjusts the voltage levels of control node signals based on the operating conditions. By optimizing voltage swings at different stages and using intermediate voltage levels (e.g., first high voltage, second high voltage, first low voltage, second low voltage), the system achieves fast transitions while minimizing the total energy required compared to using consistently high voltage swings throughout.
Solution Approach 2:
The gate driver employs dynamic voltage scaling where different voltage levels are applied at different stages of the charging process. The first, second, and third stages use different voltage configurations depending on the signal state, allowing the system to adapt voltage levels to minimize power consumption while maintaining required transition speeds.
3Reliability
If the gate driver uses more transistors to improve transition speed, then reliability improves, but device complexity increases
Solution Approach 1:
The transistor network is segmented into functional groups: level shifter transistors (first through fifth transistors) that handle voltage translation, and gate driver stage transistors (sixth through tenth transistors) that handle signal switching. This segmentation allows each group to be optimized for its specific function, achieving reliable fast transitions without requiring a monolithic complex structure.
Solution Approach 2:
The level shifter circuit serves multiple functions: it translates different voltage levels, prepares control node signals for optimal charging, and coordinates the operation of multiple transistor stages. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby limiting the increase in overall device complexity while maintaining high reliability.
Data Source
AI summary
A gate driver includes stages. Each of the stages includes a first transistor transmitting an input signal to a control node, a second transistor outputting a high gate voltage as a gate signal in response to a signal of an inverting control node, a third transistor outputting a first low gate voltage as the gate signal in response to a signal of the control node, a level shifter configured to transfer the high gate voltage or a third low gate voltage to the control node and the inverting control node in response to a signal of the control node and the signal of the inverting control node, a fourth transistor transmitting a previous carry signal to the inverting control node, and a fifth transistor outputting the high gate voltage or the third low gate voltage as a carry signal in response to the signal of the control node.