Gate Driver Line-by-Line Control for Partial Display Driving

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Solution Overview

Problem

Existing display panel driving methods are unable to control gate signals on a line-by-line basis, leading to inefficiencies in power consumption and partial driving capabilities, as they require multiple frame start indication signals for each gate line and lack line-by-line control.

Innovation Solution

A gate driver with a carry generate block, a first output block, and a second output block that selectively outputs gate initialization and gate signals based on input enable/disable signals, allowing for line-by-line control and skipping of signals for non-updating pixel rows, thereby reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple frame start indication signals are provided for each gate line to enable partial driving, then partial driving capability is improved, but device complexity increases and line-by-line control is not achieved

Engineering Contradiction:
Improvepartial driving capabilityVSAvoidnumber of control signals
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The gate driver is divided into multiple independent stages, each corresponding to a specific gate line. Each stage includes a carry generate block, first output block, and second output block that can be independently controlled. This segmentation enables line-by-line control where each stage can selectively output gate signals and gate initialization signals based on its own control inputs, achieving partial driving without requiring multiple frame start indication signals for the entire display panel.

Inventive Principle:
Principle #1Segmentation

2Reliability

If gate signals are continuously output to all gate lines, then complete display updating is ensured, but power consumption increases

Engineering Contradiction:
Improvedisplay updating completenessVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The gate driver implements periodic action by allowing stages to selectively output gate signals and gate initialization signals in a periodic manner. Each stage can be controlled to output signals only when needed for image updates, rather than continuously. The carry generate block generates carry signals periodically, and the output blocks selectively transmit gate signals based on image update requirements, reducing unnecessary signal output and lowering power consumption while maintaining complete display updating when required.

Inventive Principle:
Principle #19Periodic action

3Use of energy by moving object

If line-by-line control of gate signals is implemented, then power consumption is reduced, but control signal complexity increases

Engineering Contradiction:
Improvepower consumptionVSAvoidcontrol signal structure
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The invention merges the control functions into a unified stage-based architecture where each stage integrates a carry generate block, first output block, and second output block. This merging approach allows line-by-line control to be achieved through a regular, repeating stage structure rather than requiring individual complex control circuits for each gate line. The unified stage design reduces overall control signal complexity while enabling power-efficient line-by-line control.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9837017B2Gate driver and display device having the same
Publication Date: 2017.12.05 SAMSUNG DISPLAY CO LTD
  • US9837017B2 patent drawing
  • US9837017B2 patent drawing
  • US9837017B2 patent drawing

AI summary

A stage of a gate driver includes a carry generate block configured to output an (N)-th carry signal based on an input signal and to provide the (N)-th carry signal to an (N+1)-th stage; a first output block configured to output an (N)-th gate initialization signal based on the input signal, an input enable signal, and an input disable signal, wherein the input disable signal is inverted with respect to the input enable signal; and a second output block configured to receive the (N)-th gate initialization signal and to output an (N)-th gate signal according to the output of the (N)-th gate initialization signal; the (N)-th gate signal being delayed one horizontal period from the (N)-th gate initialization signal, wherein the gate signals and the gate initialization signals of the stages are selectively output based on the input enable signal and the input disable signal.